Electronic Design Automation Research Articles

Leveraging Public Information to Fit a Compact Hot Carrier Injection Model to a Target Technology

The design of countermeasures against integrated circuit counterfeit recycling requires the ability to simulate aging in CMOS devices. Electronic design automation tools commonly provide this ability; however, their models must be tuned for use with a specific target technology. This requires data which is ideally provided by a fab. It may also be collected from a set of purpose-built test devices, a costly and time-consuming process. Here we describe a novel, low-cost, and rapid approach to tuning such models. Our iterative method leverages public domain data sourced from published studies to fit an aging model. Results are statistically validated against the target technology’s specification. We demonstrate our approach by fitting a compact hot carrier injection degradation model for use with both core and I/O nMOSFETs from a specific 65 nm technology. Our resulting model parameter values are validated with a maximum error of 0.5% with a 99% confidence bound.

Review of Machine Learning in Logic Synthesis

Electronic design automation tools have multiple options that need to be tuned for specific designs and technology nodes. Traditionally, the tuning process is done by teams of expert engineers and demands a large amount of computational resources.In recent years, there has been an increased effort to apply machine learning techniques in electronic design automation problems, attempting to increase the design flow correlation and predictability, hence reducing the time spent on tuning.In this work, we revise modern approaches in electronic design automation and machine learning techniques applied during logic synthesis. We categorize and discuss their core technologies, such as transforming data into images. Machine learning techniques are as good as the available data. Thus, we present existing learning datasets for logic synthesis and strategies such as data augmentation to overcome the lack of specific data for logic synthesis problems.To cope with these problems, we discuss how research is shifting from traditional supervised learning techniques to reinforcement learning-based methods.

EDA: Overview and Some Trends

The development of any integrated circuit depends heavily on the quality of the EDA (Electronic Design Automation) tools used in the design flow. Improved CAD tools and algo-rithms are needed to cope with new fabrication technology requirements, advanced performance constraints, or simply the enormous number of elements involved. In this paper it is giving an overview of the importance of automation in the design process, and it is done a survey of different types of tools presenting some classifications of the tools. Then some few trends on EDA that are needed to deal with the evolution of manufacturing processes will be presented. Some optimi-zation techniques will be presented for selected physical de-sign problems (layout). An important aspect of the design is to reduce power consumption at all levels of abstraction. Power optimization is fundamental in nanoCMOS and in the IoT world. At logic and physical levels, one approach that can be used to optimize the circuit, especially reducing static leakage power and using the automatic generation of the cell layout. With on-the-fly cell generation, the same function can be implemented with a reduced number of transistors, requiring less area and significantly optimizing power and performance. Finally, the use of estimation and visualiza-tion tools is equally important. They can be applied either in the design flow or in the tool's development and research en-vironments as a way to observe and understand the behavior and interactions of algorithms and their operation on real designs and benchmarks.

Two-Level and Multilevel Approximate Logic Synthesis

Approximate computing represents a modern design paradigm that allows systems to have imprecise or inexact execution, aiming to optimize circuit area, performance, and power dissipation. The automatic construction of approximate integrated circuits (IC) is performed through computer-aided design (CAD) tools available in electronic design automation (EDA) frameworks. Approximate logic synthesis (ALS), in particular, treats two-level and multilevel topologies of combinational blocks in the development of digital IC design. This work provides a survey of ALS methods presented in the literature, from the pioneers until the state-of-the-art approaches.

Guest Editors' Words

Electronic Design Automation has been the driving force of VLSI design since those circuits are far more complex beyond what a human designer can comprehend. Today, the most advanced circuits have billions of components, mostly transistors, arranged in random logic, memory, data path, analog, mixed signal, IPs, etc. The process of automation of a large VLSI chip is extremely complex, generally decomposed into several categories and steps that are part of most existing commercial tool flows. Furthermore, timing and power optimization enable a wide range of applications we see today such as computing, mobile, internet of things (IoT), etc., and can only happen with creative innovations in EDA. For its complexity, any researcher in the field must invest heavily in finding and reading appropriate literature. In this special edition, the Journal of Integrated Circuits and Systems is collecting and surveying the key topics, algorithms and approaches that pertain to the current state-of-the-art in EDA research.

Design Automation for Emerging Technologies

After the continuous development of CMOS technology driven by transistor miniaturization and Moore’s law, the scientific community is witnessing the exploration of emerging paradigms to find new ways to develop computational systems. This paper presents critical concepts for understanding some of these new nanocomputing technologies, specifically field-coupled, quantum-dot cellular automata, nanomagnetic logic, silicon dangling bounds, photonic crystal logic, and DNA computing. Next, it shows emerging design automation tools for each of these areas and how they can be applied to support the development of new computing systems. The level of maturity and production speed of solutions achieved by conventional silicon technology thanks to very efficient electronic design automation (EDA) is remarkable. However, here we are dealing with technologies still in their infancy. Therefore, improvements in design automation tools are undoubtedly a way to accelerate the growth of new substrate alternatives and modern applications.

Enhanced chimp optimization algorithm for high level synthesis of digital filters

The HLS of digital filters is a complex optimization task in electronic design automation that increases the level of abstraction for designing and scheming digital circuits. The complexity of this issue attracting the interest of the researcher and solution of this issue is a big challenge for the researcher. The scientists are trying to present the various most powerful methods for this issue, but keep in mind these methods could be trapped in the complex space of this problem due to own weaknesses. Due to shortcomings of these methods, we are trying to design a new framework with the mixture of the phases of the powerful approaches for high level synthesis of digital filters in this work. This modification has been done by merging the chimp optimizer with sine cosine functions. The sine cosine phases helped in enhancing the exploitation phase of the chimp optimizer and also ignored the local optima in the search area during the searching of new shortest paths. The algorithms have been applied on 23-standard test suites and 14-digital filters for verifying the performance of the algorithms. Experimental results of single and multi-objective functions have been compared in terms of best score, best maxima, average, standard deviation, execution time, occupied area and speed respectively. Furthermore, by analyzing the effectiveness of the proposed algorithm with the recent algorithms for the HLS digital filters design, this can be concluded that the proposed method dominates the other two methods in HLS digital filters design. Another prominent feature of the proposed system in addition to the stated enhancement, is its rapid runtime, lowest delay, occupied area and lowest power in achieving an appropriate response. This could greatly reduce the cost of systems with broad dimensions while increasing the design speed.

POViT: Vision Transformer for Multi-Objective Design and Characterization of Photonic Crystal Nanocavities.

We study a new technique for solving the fundamental challenge in nanophotonic design: fast and accurate characterization of nanoscale photonic devices with minimal human intervention. Much like the fusion between Artificial Intelligence and Electronic Design Automation (EDA), many efforts have been made to apply deep neural networks (DNN) such as convolutional neural networks to prototype and characterize next-gen optoelectronic devices commonly found in Photonic Integrated Circuits. However, state-of-the-art DNN models are still far from being directly applicable in the real world: e.g., DNN-produced correlation coefficients between target and predicted physical quantities are about 80%, which is much lower than what it takes to generate reliable and reproducible nanophotonic designs. Recently, attention-based transformer models have attracted extensive interests and been widely used in Computer Vision and Natural Language Processing. In this work, we for the first time propose a Transformer model (POViT) to efficiently design and simulate photonic crystal nanocavities with multiple objectives under consideration. Unlike the standard Vision Transformer, our model takes photonic crystals as input data and changes the activation layer from GELU to an absolute-value function. Extensive experiments show that POViT significantly improves results reported by previous models: correlation coefficients are increased by over 12% (i.e., to 92.0%) and prediction errors are reduced by an order of magnitude, among several key metric improvements. Our work has the potential to drive the expansion of EDA to fully automated photonic design (i.e., PDA). The complete dataset and code will be released to promote research in the interdisciplinary field of materials science/physics and computer science.

Serial Biasing Technique for Electronic Design Automation in RSFQ Circuits

There has been renewed interest and efforts in increasing the complexity of superconductor circuits by means of electronic design automation (EDA). Serial biasing (SB) is a technique that reduces the total dc bias current required by large rapid single flux quantum (RSFQ) circuits, including its energy-efficient variant, ERSFQ. We believe SB needs to be incorporated in any EDA flow for large circuits. In SB, equally biased circuit blocks are placed on galvanically isolated islands and biased in series. SFQ pulses are transferred between islands by means of driver-receiver pairs (DRPs). The special current management technique, called the grapevine (GV) approach and introduced earlier, is used to handle the bias current flowing in and out of an island. In this article, we present all required layout primitives needed to implement SB for the IARPA-led SuperTools cell library that targets the SFQ5ee fab node at MIT Lincoln Laboratory. We discuss the horizontal and vertical composite driver-receiver pairs that comprise not only DRPs but also transmitters and receivers for passive transmission lines. We present the basic blocks to implement the GV managing technique for current injection and extraction. As a proof of concept, we designed a four-island test circuit that comprises all discussed layout primitives and employs an on-chip pseudorandom binary sequence generator as a test pattern source. The test circuit worked up to 50 GHz at the BER level of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> . We discuss future steps to improve the SB technique.

A Hybrid Josephson Transmission Line and Passive Transmission Line Routing Framework for Single Flux Quantum Logic

The single flux quantum (SFQ) logic family is a novel digital logic as it provides ultrafast and energy-efficient circuits. For large-scale SFQ circuit design, specialized electronic design automation (EDA) tools are required due to the differences in logic type, timing constraints, and circuit architecture, in contrast to the Complementary metal–oxide–semiconductor (CMOS) logic. In order to improve the overall performance of an SFQ circuit, an efficient routing algorithm should be applied during the layout design to perform accurate timing adjustment for fixing hold violations and optimizing critical paths. Thus, a hybrid Josephson transmission line and passive transmission line routing framework is proposed. It consists of four main modules and an exploration of the potential timing performance based on the given layout placement. The proposed routing tool is demonstrated on seven testbench circuits. The obtained results demonstrate that the operating frequency is greatly improved, and all the hold violations are eliminated for each circuit.

An equivalent circuit model of NBTI effect for short-channel P-MOSFET

An equivalent circuit model of the negative bias temperature instability (NBTI) effect in 65 nm P-MOSFET is presented in this paper. Based on an existing P-MOSFET model of a 65 nm CMOS foundry PDK (Process Design Kit) and several basic electrical components and arithmetic cells in the EDA (Electronics Design Automation) library, an equivalent circuit model for NBTI degradation has been achieved. The electrical components and arithmetic cells include voltage source, voltage-controlled voltage source, voltage-controlled current source, adder, and multiplier. The equivalent circuit model includes five tunable input parameters: gate width (W), gate length (L), temperature (temp), stress time (t), and process corner (typical/fast/slow). The model takes into account the effects of drain-source, drain-gate, and gate-source voltage stress states. The effect of process corner on NBTI is also considered. The simulation results show that the performance curve of this P-MOSFET equivalent circuit model is consistent with the measured data in some published literature. This equivalent circuit model can be utilized for long-term reliability IC design.

An online workflow scheduling algorithm considering license limitation in heterogeneous environment

AbstractWith the development of the IC industry, electronic design automation (EDA) tools are also developing. Currently, EDA tools have been migrating to high‐performance computing clusters (HPC) or the cloud to meet increasing computing and storage requirements. EDA tasks are scientific workflows, whose scheduling is a well‐known NP‐hard problem. In this paper, we propose a novel workflow scheduling algorithm HEWS, which achieves better performance through a novel hierarchical sorting method. We conducted a series of simulation experiments in different environments, and the experimental results show that our HEWS scheduling algorithm achieves better scheduling performance compared to several conventional scheduling methods, the waiting time and makespan of workflow are significantly reduced.

GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning

Electronic design automation (EDA) comprises a series of computationally difficult optimization problems that require substantial specialized knowledge as well as a considerable amount of trial-and-error efforts. However, open challenges, including long simulation runtime and lack of generalization, continue to restrict the applications of the existing EDA tools. Recently, learning-based algorithms, especially reinforcement learning (RL), have been successfully applied to handle various combinatorial optimization problems by automatically acquiring knowledge from the past experience. In this article, we formulate the floorplanning problem, the first stage of the physical design flow, as a Markov decision process (MDP). An end-to-end learning-based floorplanning framework GoodFloorplan is proposed to explore the design space, which combines graph convolutional network (GCN) and RL. Experimental results demonstrate that compared with state-of-the-art heuristic-based floorplanners, the proposed GoodFloorplan can provide better area and wirelength.

Device Parameters Based Analytical Modeling of Ground-Bounce Induced Jitter in CMOS Inverters

This article presents an analytical approach to estimate jitter in CMOS inverters in the presence of ground-bounce noise (GBN). The relationships between output and input, considering the effect of ground noise, are derived in terms of device parameters for modeling the timing variations. The deviation of each transition edge from the ideal transition edge is modeled using analytical equations to obtain peak-to-peak ground noise induced jitter. To examine the proposed modeling, five case studies are considered for covering the time domain as well as frequency domain estimations. The results obtained using the proposed methodology have a close match with those obtained from the simulations using the electronic design automation (EDA) tool. To claim the independence of proposed modeling with respect to a particular technology, the results are verified at 40, 65, and 180 nm technology nodes of United Microelectronics Corporation (UMC).

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era

In this article, we provide a comprehensive evaluation of width modulation capabilities of both nanosheet (NS) and forksheet (FS) devices, going from device level to a block level implementation. The main innovation introduced by the FS consists of a dielectric wall added between the p- and nMOS transistors. Leveraging this feature, FS shows approximately the same current behavior as NS, considered a state-of-the-art reference, but reduced parasitic capacitance thanks to its fewer but wider stacked sheets. At block level, an area reduction up to 12% is observed with FS, alongside a 13% power reduction and 10% frequency increase. Following the device comparison, the potential of sheet width modulation as additional power, performance, and area (PPA) optimization technique during synthesis and place and route (PNR) is investigated. A description of the specific steps required to enable this knob in a conventional electronic design automation (EDA) framework is provided. As demonstrated by the obtained experimental results, the same frequency of the single-width implementation can be achieved using mixed libraries with lower power consumption (13% and 16% for NS and FS, respectively), leading to improved energy efficiency. Furthermore, it is shown how designs implemented using FS benefit more from this type of optimization than the ones using NS, with a 12%–15% energy reduction compared to the 8.5%–14% obtained with NS.

AV1 Arithmetic Encoder Design on Open-Source EDA

With the increasing demand for video transmission through the Internet, video coding has become a key technology to allow this market's growth at a reduced cost. Moreover, with the inception of higher video resolutions (e.g., 4K, 8K) and their impact on video size, new video coding standards must tackle this issue to reduce video traffic demand on the global internet infrastructure. The AV1, a recently released royalties-free video coding format created by the Alliance for Open Media (AOMedia), reaches great compression rates but cannot accomplish real-time execution on software-only implementations due to its high complexity. This paper presents and analyzes AE-AV1, a high-performance 4-stage pipelined architecture to accelerate the AV1 arithmetic encoding process (part of the entropy encoder block) and make it capable of real-time execution. For the analysis, this work aims to rely on fully open-source Electronic Design Automation (EDA) tools and Package Design Kits (PDKs).

CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA)

CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA)

A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits

As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of critical importance in industries today since they are the source of most test escapes and reliability problems. Improving test quality and creating new test methods, algorithms, and test designs requires a comprehensive study of these delay defects. This article reviews the effect and impact of SDD and HDD in logic circuits. It also analyzes the relevant fault models, automatic test pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic Design Automation (EDA) tools. Based on the analysis, the benefits and drawbacks of several accessible approaches are addressed.

Characterizing and Optimizing EDA Flows for the Cloud

Design space exploration in logic synthesis and parameter tuning in physical design require a massive amount of compute resources in order to meet tapeout schedules. To address this need, cloud computing provides semiconductor and electronics companies with instant access to scalable compute resources. However, deploying electronic design automation (EDA) jobs on the cloud requires EDA teams to deeply understand the characteristics of their jobs in cloud environments. Unfortunately, there has been little to no public information on these characteristics. Thus, in this article, we first formulate the problem of moving EDA jobs to the cloud. To address the problem, we characterize the performance of four EDA main applications, namely: 1) synthesis; 2) placement; 3) routing; and 4) static timing analysis. We show that different EDA jobs require different compute configurations in order to achieve the best performance. Using observations from our characterization, we propose a novel model based on graph convolutional networks to predict the total runtime of a given stage on different configurations. Our model achieves a prediction accuracy of 87%. Furthermore, we present a new formulation for optimizing cloud deployments in order to reduce costs while meeting deadline constraints. We present a pseudopolynomial optimal solution using a multichoice knapsack mapping that reduces deployment costs by 35.29%, with minimal overhead to the total runtime. In addition, we describe a cloud-ready solution, called EDA analytics central, for the continuous optimization of a design across an EDA flow. We used this system in building our runtime prediction model.

Simulated Annealing Particle Swarm Optimization for a Dual-Input Broadband GaN Doherty Like Load-Modulated Balance Amplifier Design

In this brief, an automatic power amplifier (PA) design system based on simulated annealing particle swarm optimization (SA-PSO) algorithm is proposed to perform multi-objective optimization in designing broadband Doherty like load-modulated balanced amplifier (LMBA). Specifically, by combining the programming environment with commercial electronic design automation (EDA) software, the optimization process can be implemented automatically. Then, complex and rigorous impedance trajectory aligning at different power levels can be easily obtained using the proposed optimization algorithm, demonstrating the automatic PA design system’s superiority over the built-in optimizer in commercial EDA software for designing broadband Doherty like LMBA. A 2.5-3.5 GHz dual-input Doherty like LMBA is simulated and measured, showing a saturated output power of 45.4-48.2 dBm, a saturation drain efficiency of 60.7% - 69.7%, a 6 dB power back-off DE of 59.2% - 65.8%, and a 9 dB power back-off DE of 52.7% - 66.9%.