Electronic System Level Design Research Articles

Fast Loosely-Timed Deep Neural Network Models with Accurate Memory Contention

The emergence of data-intensive applications, such as Deep Neural Networks (DNN), exacerbates the well-known memory bottleneck in computer systems and demands early attention in the design flow. Electronic System-Level (ESL) design using SystemC Transaction Level Modeling (TLM) enables effective performance estimation, design space exploration, and gradual refinement. However, memory contention is often only detectable after detailed TLM-2.0 approximately-timed or cycle-accurate RTL models are developed. A memory bottleneck detected at such a late stage can severely limit the available design choices or even require costly redesign. In this work, we propose a novel TLM-2.0 loosely-timed contention-aware (LT-CA) modeling style that offers high-speed simulation close to traditional loosely-timed (LT) models, yet shows the same accuracy for memory contention as low-level approximately-timed (AT) models. Thus, our proposed LT-CA modeling breaks the speed/accuracy tradeoff between regular LT and AT models and offers fast and accurate observation and visualization of memory contention. Our extensible SystemC model generator automatically produces desired TLM-1 and TLM-2.0 models from a DNN architecture description for design space exploration focusing on memory contention. We demonstrate our approach with a real-world industry-strength DNN application, GoogLeNet. The experimental results show that the proposed LT-CA modeling is 46x faster in simulation than equivalent AT models with an average error of less than 1% in simulated time. Early detection of memory contentions also suggests that local memories close to computing cores can eliminate memory contention in such applications.

Analyzing Variable Entanglement for Parallel Simulation of SystemC TLM-2.0 Models

The SystemC TLM-2.0 standard is widely used in modern electronic system level design for better interoperability and higher simulation speed. However, TLM-2.0 has been identified as an obstacle for parallel SystemC simulation due to the disappearance of channels. Without a containment construct, simulation threads are permitted to directly access data of other modules and that makes it difficult to synchronize such accesses as required by the SystemC execution semantics. In this paper, we propose a compile time approach to statically analyze potential conflicts among threads in SystemC TLM-2.0 loosely- and approximately-timed models. We introduce a new Socket Call Path technique which provides the compiler with socket binding information for precise static analysis. We also propose an algorithm to analyze entangled variable pairs. Experimental results show that our approach is able to support automatically safe parallel simulation of SystemC models with TLM-2.0 Blocking Transport Interface, Direct Memory Interface and Non-blocking Transport Interface, resulting in impressive simulation speeds.

SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems

This work faces the problem of the Electronic System-Level (ESL) HW/SW co-design of dedicated electronic digital systems based on heterogeneous multi-processor architectures. In particular, the work presents a prototype SystemC-based environment that exploits a Design Space Exploration (DSE) approach able to suggest an HW/SW partitioning of the system specification and a mapping onto an automatically defined architecture. The descriptions of the reference HW/SW co-design methodology and the main design issues related to the developed DSE SW tools, supported by two reference use cases that allows to understand the role of the DSE step in the whole design flow, represent the core of the paper.

Automated Generation of Synchronous Formal Models from SystemC Descriptions

SystemC is one of the most popular electronic system-level design language and it is embraced by a growing community that seeks to move to a higher level of abstraction. It lacks however a standard way of integrating formal methods and formal verification techniques into a SystemC design flow. In this paper, we show how SystemC descriptions are automatically transformed into the formal synchronous language Signal, while conserving the original structure and enabling the application of formal verification techniques. Signal provides a simple semantics of concurrency and time, and allows verification with an existing theorem prover and model checker. The approach that we propose consists of two steps: the extraction of the structure and the transformation of the behavior. In the first step, SystemC model is analyzed and the structural information is extracted. In the second step, for each SystemC module, the corresponding Signal behavior is generated and filled into the already prepared Signal structure.

PSK Transciever designing using SystemVue

Since, the industrial electronics is trending towards more compact components and system integration, innovative products offering greater flexibility, quality, safety, reliability, energy savings, wide range of connectivity with long operating lifetime. Now, Electronics is widely used in information processing, telecommunication and signal processing. Due to the complex nature of electronics theory, laboratory experimentation is an important part of development of electronic devices. These experiments are used to test or verify the proposed design and detect errors. Historically, electronics labs have consisted of electronic devices and equipment located in the physical space. Although in more recent years, the trend has been towards electronics lab simulation softwares and SystemVue is also one of them. SystemVue is a focussed electronic design automation (EDA) environment for electronic system-level (ESL) design. It enables system architects and algorithm developers to innovate the physical layer (PHY) of wireless and aerospace/defence communication systems and provide unique value to RF, DSP and FPGA/ASIC implementers. As a dedicated platform for ESL design and signal processing realization, SystemVue replaces general-purpose digital, analog and math environments. SystemVue “speaks RF”, cuts PHY development and verification time in half and connects to your mainstream EDA flow.

Equivalence Checking of Scheduling in High-Level Synthesis Using Deep State Sequences

By using high-level synthesis tools, electronic system level design provides a promising solution to fill the growing design productivity gap of high quality hardware systems. However, an error may exist in the implementation of a compiler due to the complex and error prone compiling process. Equivalence checking is the process of proving that the target code is a correct translation of the source code being compiled. In this paper, we present a novel approach to solve the false-negative problem of value propagation (VP) based equivalence checking method. Finite State Machine with Datapath (FSMD) is used to model the original and the transformed programs. Our method proves the equivalence by comparing the deep state sequences (DSS) between the original and the transformed FSMD. Automatic test vector generation (ATVG) and simulation technique are used to recognize the corresponding DSS and exclude the false paths to solve the false-negative problem. The promising experimental results show the effectiveness of the proposed method to solve the false-negative problem in VP based equivalence checking method.

Automated Nonintrusive Analysis of Electronic System Level Designs

Due to the ever increasing complexity of hardware systems, designers strive for higher levels of abstractions in the early stages of the design process. Modeling hardware at the electronic system level (ESL) is one way to address this demand, with the C++-based system modeling framework SystemC and its abstract communication library transaction level modeling (TLM) having become de-facto standards for ESL system design. While the C++ compiler is sufficient to compile and simulate a given ESL design, for tasks of design understanding, debugging, or validation (where access to the details of design’s structure and behavior is necessarily required), design needs to be processed by an appropriate tool. This problem is often solved by adding instrumentation code to either the design or the library, usually resulting in incomplete logs, work overhead and/or incompatibilities. This paper introduces an approach that automatically extracts information about both, structure and behavior of SystemC designs and TLM transactions, nonintrusively. The information is retrieved from a given design by running it in debug mode while being connected to a preprogrammed debugger, thus leaving the existing sources and workflows untouched while collecting a vast amount of data without user intervention. Illustrating use cases, value change dump files of the SystemC models’ behavior and unified modeling language activity diagrams of transaction protocols are created automatically from simulation runs.

Leakage Models for High-Level Power Estimation

Leakage currents are one major concern when designing recent CMOS devices, making design for leakage at all stages of the design process mandatory. Early leakage optimization requires early leakage prediction, and for electronic system level design, this means estimation capabilities at register transfer (RT) level or above. Existing models are very accurate, but slow [transistor level such as Berkeley Simulator (BSIM)], or the slightly faster gate level models (such as the Liberty library), disregard relevant parameters. We present RT level leakage macro models, which are faster than recent gate level models, while preserving the accuracy of the transistor level models to a great extent. An estimation framework is proposed, describing the subthreshold, gate, and junction leakage of recent technology devices. The models are characterized using BSIM compact models and a Monte Carlo process variation description. Each varying BSIM parameter can be described. As an example of use, channel length, oxide thickness, and channel doping are regarded together with the temperature, supply voltage and body voltage. The final macro model needs less than a hundred parameters to capture the leakage behavior of an entire RT component and is still analytically describing the dependence to the process parameters. Compared to SPICE + BSIM, a model prediction is computed up to a hundred times faster for large RT components, and is, depending on the analyzed technology, within 2.1% (for 16-nm LP)–6.8% (for 65-nm bulk) deviation over a wide range of operating conditions and process variation settings.

Methodology for developing virtual platforms from power‐aware to power‐ and thermal‐aware at electronic system level

With the growth of complex multiprocessor system-on-chip design and the evolution of process technology, it is crucial to address thermal issues owing to the high-power density of chips. Electronic system level (ESL) design is an acknowledged effective methodology to explore system design by virtual platforms (VPs) at the early stages of integrated circuit (IC) design. Therefore, power- and thermal-aware (PTA) VPs at the ESL are required to explore the thermal issues at the early stages of IC design. Current VPs at the ESL are less discussed in the thermal issues. Therefore, the authors propose a methodology to easily develop VPs from power awareness to power and thermal awareness. In the methodology, a refined thermal engine that has lower computational complexity is proposed to analyse the heat of ICs, and it has high compatibility for integration with power-aware (PA) VPs. In addition, the thermal analysis in the methodology considers the thermal effects of leakage power consumption to reflect the physical temperature of ICs. Thus, system designers can utilise the proposed methodology to easily develop their PA VPs into PTA VPs.

Performance Analysis of Weakly-Consistent Scenario-Aware Dataflow Graphs

The timed dataflow model of computation is a useful performance analysis tool for electronic system level design automation and embedded software synthesis. Its determinism gives it strong analyzability properties. Its monotonic temporal behavior provides hard real-time guarantees on throughput and latency. It is expressive enough to cover a large class of applications and platforms. The trend however, in both embedded applications and their platforms is to become more dynamic, reaching the limits of what the model can express and analyze with tight performance guarantees. Scenario-aware dataflow (SADF) allows more dynamism to be expressed, introducing a controlled amount of non-determinism into the model to represent different scenarios of behavior. We investigate so-called weakly consistent graphs in which the scenario changes are not tightly coupled with periods of repetitive behavior of the static dataflow behavior in scenarios as in previous methods. We define the semantics of such graphs in terms of (max , +)-algebra and we introduce a method to analyze throughput using a generalization of (max , +)-automata. We show that weakly-consistent SADF generalizes many of the existing analyzable dynamic dataflow models, such as CSDF, PDF and CFDF and we present an algorithm to convert CSDF graphs to SADF.

Belling the CAD: Toward Security-Centric Electronic System Design

In order to keep pace with the growing complexity of integrated circuits (ICs), IC and system designers are increasingly using electronic system level (ESL) design tools. ESL tool sales were around $460 million in 2011. The value of the ICs designed using these tools is at least an order of magnitude more. Concurrently, advanced IC reverse engineering techniques are being developed and used by attackers. In response, several anti-reverse engineering techniques have been proposed for integration into the IC design flow. An important class of defenses hardens the controllers that orchestrate the functionality of designs generated by ESL tools. We demonstrate an attack to recover the controller in any ESL-generated design even if the controller has been hardened using state-of-the-art controller hardening techniques. The attack analyzes the unhardened parts of the controller (i.e., the controller output logic and datapath) and reconciles this information with the architectural, controller, and timing constraints implicit in and underlying all ESL design methodologies. We then propose a countermeasure that inserts decoy connections into an ESL tool-generated design to thwart reverse engineering. We introduce a security metric to quantify the effectiveness of the developed attacks and defenses. We demonstrate the attack and defenses on designs generated by state-of-the-art ESL tools.

System‐level assertions: approach for electronic system‐level verification

As design of digital systems become more complex and more transistors are incorporated into a single chip, design and verification methodologies moves into higher levels. Now that design at the register transfer level (RTL) has reached its maturity, the focus is shifting to electronic system level (ESL) design tools, languages and methodologies. At the centre of this and perhaps the most challenging are verification methods and tools to use for verifying designs at the ESL. This study presents a new concept of system-level assertions for ESL verification. It also demonstrates an environment for functionally verifying system-level designs using these system-level assertions. The proposed environment adapts existing EDA simulation tools, which are mainly used for RTL design and verification, and utilises them for system-level verification. In this environment, designs are modelled in SystemC-transaction level modelling 2.0, and assertions are written in SystemVerilog. Design and verification parts are connected together using SystemVerilog Direct Programming Interface mechanism, and designs that are described in SystemC are verified against system-level assertions in the course of SystemVerilog simulation.

Transaction-level power analysis of VLSI digital systems

The increasing complexity of VLSI digital systems has dramatically supported system-level representations in modeling and design activities. This evolution makes often necessary a compliant rearrangement of the modalities followed in validation and analysis tasks, as in the case of power performances estimation.Nowadays, transaction-level paradigms are having a wider and wider consideration in the research on electronic system-level design techniques. With regard to the available modeling resources, the most relevant framework is probably the transaction-level extension of the SystemC language (SystemC/TLM), which therefore represents the best platform for defining transaction-level design techniques.In this paper we present a macro-modeling power estimation methodology valid for SystemC/TLM prototypes and of general applicability. The present discussion illustrates the implementation modalities of the proposed approach, verifying its effectiveness through a comparison with RTL estimation techniques.

Using ACL2 to Verify Loop Pipelining in Behavioral Synthesis

Behavioral synthesis involves compiling an Electronic System-Level (ESL) design into its Register-Transfer Level (RTL) implementation. Loop pipelining is one of the most critical and complex transformations employed in behavioral synthesis. Certifying the loop pipelining algorithm is challenging because there is a huge semantic gap between the input sequential design and the output pipelined implementation making it infeasible to verify their equivalence with automated sequential equivalence checking techniques. We discuss our ongoing effort using ACL2 to certify loop pipelining transformation. The completion of the proof is work in progress. However, some of the insights developed so far may already be of value to the ACL2 community. In particular, we discuss the key invariant we formalized, which is very different from that used in most pipeline proofs. We discuss the needs for this invariant, its formalization in ACL2, and our envisioned proof using the invariant. We also discuss some trade-offs, challenges, and insights developed in course of the project.

Multi-core system performance prediction and analysis at the ESL

Multi-core system and the associated software parallelisation techniques have become one of the major trends of SoC design. For higher system performance and lower power consumption, this paper reveals a system performance prediction and analysis method for multi-core system by adopting electronic system-level ESL design methodology. With the high simulation speed and approximate time characteristic, the ESL virtual platform can be done at early design stage before implementation on the real chip. Based on the scalable multi-core virtual platform, we can perform one to eight-core system performance trend prediction as well as multi-core system performance analysis. The software parallelisation experiments are conducted for observing the performance improvement and further discussed about hardware-software co-design and the hardware cost reduction benefited from increasing software parallelism.

A novel intelligent verification platform based on a structured analysis model

An intelligent verification platform based on a structured analysis model is presented. Using an abstract model mechanism with specific signal interfaces for user callback, the unified structured analysis data, shared by the electronic system level design, functional verification, and performance evaluation, enables effi- cient management review, auto-generation of code, and modeling in the transaction level. We introduce the class tree, flow parameter diagram, structured flow chart, and event-driven finite state machine as structured analysis models. As a sand table to carry maps from different perspectives and levels via an engine, this highly reusable platform provides the mapping topology to search for unintended consequences and the graph theory for comprehensive coverage and smart test cases. Experimental results show that the engine generates efficient test sequences, with a sharp increase in coverage for the same vector count compared with a random test.

Towards automated implementation of adaptive systems from abstract SystemC specifications

Adaptivity is a key feature in embedded systems which requires explicit support in Electronic System-Level (ESL) design methodologies. Similarly, a higher level of abstraction during system specification is crucial for enabling ESL design activities such as Design Space Exploration. This has motivated the development of methodologies, such as A-HetSC, for enabling SystemC abstract specification of the adaptive parts of a system. However, in order to enable practical ESL design flows, it is essential to enable suitable implementation paths from the abstract adaptive specification. Otherwise, the cost of manual refinement of the abstract adaptive specification or simply the inability to systematically achieve an implementation will compromise the advantages obtained by the abstract model. This paper presents a system-level implementation methodology for tackling the implementation of the adaptive parts of an abstract SystemC specification. These adaptive parts are described as abstract adaptive processes, the basic constructs for specifying adaptivity in the A-HetSC methodology. The methodology proposes two main implementation paths. One path automatically targets an embedded SW implementation, for an immediate, flexible and cheap implementation of the adaptive processes. For the HW implementation path, a systematic SystemC-based refinement for targeting a refined model is proposed. Such a refined model is already supported by high-level synthesis tools, which automate the rest of the HW implementation path. It enables a cost efficient implementation of adaptive functionality in contexts where a software implementation does not fulfil time performance demands. The refinement of an adaptive inverse transform module, as part of an adaptive video decoder (AVD), is used as a demonstrative example.

Automatic TLM Fault Localization for SystemC

To meet today's time-to-market demands, catching bugs as early as possible during the design of a system is essential. In electronic system level design where SystemC has become the de-facto standard due to transaction level modeling (TLM), many approaches for verification have been developed. They determine an error trace that demonstrates the difference between the required and the actual behavior of the system. However, the subsequent debugging process is very time-consuming, in particular due to TLM-related faults caused by complex process synchronization and concurrency. In this paper, we present an automatic fault localization approach for SystemC TLM designs. We target typical TLM faults, such as accidentally swapped blocking and nonblocking transactions, erroneous event notification, or incorrect transaction data. The approach determines parts of the design that can be changed such that the intended behavior of the design is obtained by removing the contradiction given by the error trace. Single, as well as multiple faults, is considered. Techniques based on bounded model checking are used to find the faulty parts. We demonstrate the quality of our approach by several experiments. As shown in the experiments, the fault locations are identified very fast and hence a significant acceleration for the design of SystemC TLM models is achieved.

On the interfacing between QEMU and SystemC for virtual platform construction: Using DMA as a case

In this paper, we present an interface for the hardware modeled in SystemC to access those modeled in QEMU on a QEMU and SystemC-based virtual platform. By using QEMU as the instruction-accurate instruction set simulator (IA-ISS) and its capability to run a full-fledged operating system such as Linux, the virtual platform with the proposed interface can be used to facilitate the co-design of hardware models and device drivers at the early stage of Electronic System Level (ESL) design flow. In other words, by using such a virtual platform, the hardware models and associated device drivers can be cross verified while they are being developed so that malfunctions in the hardware models or the device drivers can be easily detected. Moreover, the virtual platform with the proposed interface is capable of providing statistics of instructions executed, memory accessed, and I/O performed at the instruction-accurate level—thus not only making it easy to evaluate the performance of the hardware models but also making it possible for design space exploration.

Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections

The ever-increasing design complexity of modern digital systems makes it necessary to develop electronic system-level (ESL) methodologies with automation and optimization in the higher abstraction level. How the concurrency is modeled in the application specification plays a significant role in ESL design frameworks. The state-of-art concurrent specification models are not suitable for modeling task-level concurrent behavior for the hardware synthesis design flow. Based on the concurrent collection (CnC) model, which provides the maximum freedom of task rescheduling, we propose task-level data model (TLDM), targeted at the task-level optimization in hardware synthesis for data processing applications. Polyhedral models are embedded in TLDM for concise expression of task instances, array accesses, and dependencies. Examples are shown to illustrate the advantages of our TLDM specification compared to other widely used concurrency specifications.