Equivalence Checking of Scheduling in High-Level Synthesis Using Deep State Sequences

Jian Hu,Guilin Chen,Xianglin Wei,Guanwu Wang

doi:10.1109/access.2019.2960511

Abstract

By using high-level synthesis tools, electronic system level design provides a promising solution to fill the growing design productivity gap of high quality hardware systems. However, an error may exist in the implementation of a compiler due to the complex and error prone compiling process. Equivalence checking is the process of proving that the target code is a correct translation of the source code being compiled. In this paper, we present a novel approach to solve the false-negative problem of value propagation (VP) based equivalence checking method. Finite State Machine with Datapath (FSMD) is used to model the original and the transformed programs. Our method proves the equivalence by comparing the deep state sequences (DSS) between the original and the transformed FSMD. Automatic test vector generation (ATVG) and simulation technique are used to recognize the corresponding DSS and exclude the false paths to solve the false-negative problem. The promising experimental results show the effectiveness of the proposed method to solve the false-negative problem in VP based equivalence checking method.

Highlights

High-level synthesis (HLS) is generally a process of translating a source code into a target code, often with an objective to save critical resources and/or reduce the execution time
The symbolic simulator and Finite State Machine with Datapath (FSMD) extractor are implemented based on Pycparser [20]
The second and the third columns show the number of states in the original FSMD and loops in the original program

Summary

Introduction

High-level synthesis (HLS) is generally a process of translating a source code into a target code, often with an objective to save critical resources and/or reduce the execution time. It can make the programmer write an efficient code and focus only on the correctness and functionality of the program being developed. Scheduling, one of subtasks in HLS, assigns operations of a behavior description with specific clock cycles based on given constraints of area, delay and data dependencies. Code motion based optimizations [2]–[5] are used in the scheduling phase of HLS tools to improve the quality of synthesis results. It is necessary to validate the functional equivalence between the input program to HLS (i.e., source code) and the scheduled program generated by HLS (i.e., transformed code)

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Conclusion