Electronic Integrated Circuits Research Articles

Stabilization of Tetragonal Phase in Hafnium Zirconium Oxide by Cation Doping for High-K Dielectric Insulators.

As electronic circuit integration intensifies, there is a rising demand for dielectric insulators that provide both superior insulation and high dielectric constants. This study focuses on developing high-k dielectric insulators by controlling the phase of the Hf0.5Zr0.5O2 (HZO) film with additional doping, utilizing yttrium (Y), tantalum (Ta), gallium (Ga), silicon (Si), and aluminum (Al) as dopants. Doping changes the ratio of tetragonal to monoclinic phases in doped HZO films, and Y-doped HZO (Y:HZO) films specifically exhibit a high tetragonal phase ratio and a dielectric constant of 40.9, indicating superior insulating properties compared to undoped HZO films. To clarify the fundamental mechanism driving the enhancement in dielectric properties, we have carried out various analyses combined with density functional theory (DFT) calculations. Through the optimization of the post-deposition annealing (PDA) process and the heterojunction structure with Al2O3, an Al2O3/Y:HZO heterojunction with a high dielectric constant and even lower leakage current compared to a single layer was developed. The thin-film transistor (TFT) with the Au/Ti/amorphous InGaZnO4 (a-IGZO)/Al2O3/YHZO/TiN heterojunction structure exhibits low subthreshold swing (SS) values within a narrow gate-source voltage (Vsg) range. This study advances knowledge on how the controlled-phase doped HZO films affect the dielectric constant and leakage current and will contribute to semiconductor technology advancements by overcoming the limitations of conventional high-k dielectric insulators.

Optimization of cooling process under varied pulsed conditions in multi-stage thermoelectric systems

This paper addresses the issue of thermoelectric cooling in a pulsed quasi-steady state (repetitive) condition. This situation occurs, for example, for an electronic integrated circuit performing demanding tasks in a discontinuous manner. Using heat reservoirs of selected capacity that are part of the thermoelectric system and appropriate shaping of the time profile of the supplied electrical current, cooling temperatures not achievable in the steady state for the system can be reached in a pulsed manner for a specified period. This process is subject to optimisation. The analysis was carried out for a two-stage system with an internal (interstage) heat reservoir of a given thermal capacity. The aim of the study was to find the relationship between the level of the supercooling temperature, its repeatability and the ability to maintain this temperature for a given time. To this end, two supply current waveforms were adopted and optimised both without and with contact thermal resistance in the system. The lowest subcooling temperature of about 7 K lower than the steady-state temperature was obtained for a very long period and a very short holding time. Decreasing the period or increasing the holding time results in a non-linear increase in temperature. Similar effects are obtained for the contact thermal resistance present in each layer. A full map of the period-thermal resistance–temperature relationship was determined, as well as the supercooling potential curves.

PHOTONIC INTEGRATED CIRCUITS: GIANT LEAP IN COMPUTING TECHNOLOGY

There is a continued demand for increase in computing requirements from sensor, smartphones, to servers. However, the technology improvements in clock speed, power, and memory bandwidth from traditional electronic integrated circuits (EIC) has started to saturate. This has triggered further research in exploration of photon integrated circuits (PIC) that utilize photons (or particles of light) as opposed to electrons to form a functioning circuit. Research suggests that by integrating the benefits of EIC and PIC, one is able to harness the best of both worlds. The inherent advantages of photonics technology such as speed, energy-efficiency, and density, coupled with the advances in material technology, make them suitable to address the challenge of designing heterogeneous chips. This paper presents the fundamentals of the photonic technology, applicability to solving digital computing problems, ability to integrate into PICs, and its capability to complement electronic integrated circuits for powering the computing demands of emerging applications.

Iterative printing of bulk metal and polymer for additive manufacturing of multi-layer electronic circuits

In pursuing advancing additive manufacturing (AM) techniques for 3D objects, this study combines AM techniques for bulk metal and polymer on a single platform for one-stop printing of multilayer 3D electronic circuits with two novel aspects. The first innovation involves the embedded integration of electronic circuits by printing low-resistance electrical traces from bulk metal into polymer channels. Cross-section grinding results reveal (92 ± 5)% occupancy of electrically conductive traces in polymer channels despite the different thermal properties of the two materials. The second aspect encompasses the possibility of printing vertical bulk metal vias up to 10 mm in height with the potential for expansion, interconnecting electrically conductive traces embedded in different layers of the 3D object. The work provides comprehensive 3D printing design guidelines for successfully integrating fully embedded electrically conductive traces and the interconnecting vertical bulk metal vias. A smooth and continuous workflow is also introduced, enabling a single-run print of functional multilayer embedded 3D electronics. The design rules and the workflow facilitate the iterative printing of two distinct materials, each defined by unique printing temperatures and techniques. Observations indicate that conductive traces using molten metal microdroplets show a 12-fold reduction in resistance compared to nanoparticle ink-based methods, meaning this technique greatly complements multi-material additive manufacturing (MM-AM). The work presents insights into the behavior of molten metal microdroplets on a polymer substrate when printed through the MM-AM process. It explores their characteristics in two scenarios: When they are deposited side-by-side to form conductive traces and when they are deposited out-of-plane to create vertical bulk metal vias. The innovative application of MM-AM to produce multilayer embedded 3D electronics with bulk metal and polymer demonstrates significant potential for realizing the fabrication of free-form 3D electronics.

Glass interposer for heterogeneous integration of flip-chipped photonic and electronic integrated circuits

Glass interposer for heterogeneous integration of flip-chipped photonic and electronic integrated circuits

Magnetization reversal by multiple optical pulses for a photonic spiking neuron with the leaky integrate and fire model

Photonic accelerators are anticipated to be the next generation of hardware processors, replacing traditional electronic accelerators. In current photonic accelerators based on artificial neural networks, photonic integrated circuits are incorporated with electronic integrated circuits to leverage their strengths: photonic circuits are used to perform linear calculations, while electronic circuits are used to perform nonlinear calculations. However, this architecture requires optoelectric conversion at each layer and is unable to leverage the superiority of light. We propose a novel photonic spiking neuron with a magneto-optical synapse and an all-optical spiking neural network. This study experimentally demonstrates that the magnetization reversal of CoFeB, which occurs during thermal accumulation owing to multiple optical pulses, is similar to the behavior of the leaky integrated and fire model of spiking neurons.

MAG-PUFs: Authenticating IoT devices via electromagnetic physical unclonable functions and deep learning

The challenge of authenticating Internet of Things (IoT) devices, particularly in low-cost deployments with constrained nodes that struggle with dynamic re-keying solutions, renders these devices susceptible to various attacks. This paper introduces a robust alternative mitigation strategy based on Physical-Layer Authentication (PLA), which leverages the intrinsic physical layer characteristics of IoT devices. These unique imperfections, stemming from the manufacturing process of IoT electronic integrated circuits (ICs), are difficult to replicate or falsify and vary with each function executed by the IoT device. We propose a novel lightweight authentication scheme, MAG-PUFs, that uses the unintentional Electromagnetic (EM) emissions from IoT devices as Physical Unclonable Functions (PUFs). MAG-PUFs operate by collecting these unintentional EM emissions during the execution of pre-defined reference functions by the IoT devices. The authentication is achieved by matching these emissions with profiles recorded at the time of enrollment, using state-of-the-art Deep Learning (DL) approaches such as Neural Networks (NN) and Autoencoders. Notably, MAG-PUFs offer compelling advantages: (i) it preserves privacy, as it does not require direct access to the IoT devices; and, (ii) it provides unique flexibility, permitting the selection of numerous and varied reference functions. We rigorously evaluated MAG-PUFs using 25 Arduino devices and a diverse set of 325 reference function classes. Employing a DL framework, we achieved a minimum authentication F1-Score of 0.99. Furthermore, the scheme’s efficacy in detecting impostor EM emissions was also affirmed, achieving a minimum F1-Score of 0.99. We also compared our solution to other solutions in the literature, showing its remarkable performance. Finally, we discussed code obfuscation techniques and the impact of Radio Frequency (RF) interference on the IoT authentication process.

A Bi-CMOS electronic photonic integrated circuit quantum light detector.

Complimentary metal-oxide semiconductor (CMOS) integration of quantum technology provides a route to manufacture at volume, simplify assembly, reduce footprint, and increase performance. Quantum noise-limited homodyne detectors have applications across quantum technologies, and they comprise photonics and electronics. Here, we report a quantum noise-limited monolithic electronic-photonic integrated homodyne detector, with a footprint of 80 micrometers by 220 micrometers, fabricated in a 250-nanometer lithography bipolar CMOS process. We measure a 15.3-gigahertz 3-decibel bandwidth with a maximum shot noise clearance of 12 decibels and shot noise clearance out to 26.5 gigahertz, when measured with a 9-decibel-milliwatt power local oscillator. This performance is enabled by monolithic electronic-photonic integration, which goes below the capacitance limits of devices made up of separate integrated chips or discrete components. It exceeds the bandwidth of quantum detectors with macroscopic electronic interconnects, including wire and flip chip bonding. This demonstrates electronic-photonic integration enhancing quantum photonic device performance.

High-quality single InGaAs/GaAs quantum dot growth on a silicon substrate for quantum photonic applications

Developing non-classical light sources for use in quantum information technology is a primary goal of quantum nanophotonics. Significant progress has been made in this area using quantum dots grown on III/V semiconductor substrates. However, it is crucial to develop quantum light sources based on silicon wafers to facilitate large-scale integration of electronic circuits and quantum photonic structures. We present a method for the direct heteroepitaxial growth of high-quality InGaAs quantum dots on silicon, which enables the fabrication of scalable and cost-effective quantum photonics devices that are compatible with silicon technology. To achieve high-quality GaAs heterostructures, we apply an intermediate GaP buffer and defect-reducing layers on a silicon substrate. The epitaxially grown quantum dots exhibit optical and quantum-optical properties similar to reference ones based on conventional GaAs substrates. The distributed Bragg reflector used as a backside mirror enables us to achieve bright emission with up to (18 ± 1)% photon extraction efficiency. Additionally, the quantum dots exhibit strong multi-photon suppression with g(2)(τ) = (3.7 ± 0.2) × 10−2 and high photon indistinguishability V = (66 ± 19)% under non-resonant excitation. These results indicate the high potential of our heteroepitaxy approach in the field of silicon-compatible quantum nanophotonics. Our approach can pave the way for future chips that combine electronic and quantum photonic functionality.

Recent Progress in Nanophotonic Light Sources

It is increasingly crucial in the information era to rapidly transmit and process vast quantities of data. However, conventional electronic integrated circuits that operate at rates below 10 GHz encounter significant challenges in effectively managing parallel signals. How can information be transmitted more quickly? Photonic integrated circuits (PICs) are the solution. PICs have the capability of processing multiple signals in parallel on a single optical waveguide by multiplexing wavelength, polarization, and angular momentum. This enables PICs to transmit at speeds exceeding 100 GHz, showing the potential to increase processing speeds while simultaneously reducing power levels. Nevertheless, one drawback of photonic devices is that they are typically several orders of magnitude larger than electronic devices. Consequently, nanophotonics researchers have been working to make photonic devices smaller without compromising their ability to control light. Advances in nanoscale light sources can present a viable solution to overcome these obstacles. With the formation of long-lasting, spatially confined resonances in nanocavities, it is possible to precisely manipulate far-field radiation. In this article, we provide an overview of the recent achievements in nanophotonic light sources, including topological nanolasers and single-photon emitters.

Mixing Materials for Integrated Photonic Innovation

Photonics, an ever-growing field since the invention of lasers in the 1960s, has been applied in wide-ranging applications such as optical communications, sensing, imaging and more. Photonic integrated circuits (PIC) are the next step to take this technology and shrink it onto a semiconductor chip, leading to more compact, cheaper, and lower power consumption solutions. However, integrated photonics faces the challenge of lacking a single material platform that encompasses all the desired properties, unlike its more mature electronic integrated circuit counterpart which uses silicon with a standardised fabrication process known as complementary metal oxide semiconductor (CMOS). To overcome this limitation, researchers are exploring hybrid and heterogeneous integration techniques. By combining the strengths of different photonic platforms, such as III-V materials for light emission, silicon for strong light guidance, silicon-nitride for visible light guiding, and lithium niobate for its modulating capabilities, integrated photonic technologies can harness the collective advantages and unlock new possibilities. “Light brings us the news from the universe.” — Sir William Bragg

태국시장에서 한국 수출상품의 국제경쟁력에 관한 연구

Purpose – The purpose of this study is to analyze the competitiveness of Korea’s export products against China, Japan, and Malaysia in the Thai market. Design/Methodology/Approach – The analysis tools used were RCA and TSI to the world and Thailand. Trade volume data was extracted using the UN Comtrade DB for 5 years (2018 to 2022) between Korea and its competitors. Through this analysis, this study examines how each country's competitiveness has changed and presents implications. Findings – The international competitiveness of Korean export products in the Thai market was analyzed using RCA and TSI indices with those of China, Japan, and Malaysia. As a result, Korea's products that were competitive in the global market and those that were competitive in the Thai market showed conflicting results. Products from China, Japan, and Malaysia also showed similar competitiveness. Research Implications – Regarding the degree of TSI in the global market for the analyzed items, Korea has an advantage in items in which it is traditionally strong, such as HS 8542 electronic integrated circuits and HS 8708 automobile parts. In the Thai market, items such as HS 7403 refined copper and copper alloy and HS 3304 cosmetics show strong performance.

Low-temperature process design for inversion mode n-channel thin-film-transistor on polycrystalline Ge formed by solid-phase crystallization

We fabricated an inversion mode n-channel thin-film-transistor (TFT) on polycrystalline (poly-) Ge at low temperatures for monolithic three-dimensional large-scale IC (3D-LSI) and flexible electronics applications. Based on our previously reported solid-phase crystallization (SPC) method, we designed an n-channel TFT fabrication process with phosphorous ion implantation to provide the source/drain (S/D). We succeeded in fabricating an n-channel TFT with typical electrical characteristics on poly-Ge and confirmed its operation mode to be inversion mode. However, the fabrication process included a high temperature (500 °C) step for S/D activation. To reduce the process temperature, we used a metal-induced dopant activation method and successfully reduced the activation temperature to 360 °C. This combination is expected to pave the way for high-performance 3D-LSI and flexible electronic devices based on SPC-Ge.

(Invited) Wafer Bonding for MEMS Integration and Packaging

Wafer bonding is a critical manufacturing process for a vast number of experimental and commercial microelectromechanical system (MEMS) devices [1-5]. Wafer bonding is used for both the hermetic sealing of MEMS [3-5], and for integrating MEMS with electronic integrated circuits (IC) [1-2]. In this invited talk we present recent examples of wafer bonding approaches targeted at hermetic sealing of emerging MEMS devices such as silicon photonic MEMS [3, 4]. In these processes, the MEMS are sealed by wafer bonding and transferring individual lids, while at the same time keeping the final total die thickness as thin as possible. Furthermore, we also present examples of wafer bonding techniques targeted at integrating MEMS or nanoelectromechanical systems (NEMS) directly on top of electronic integrated circuits (IC), thereby closely packaging the MEMS devices with the electronic circuits that provide an interface to the outside world [1-2]. Ultimately the presented wafer bonding approaches can contribute to further miniaturization and thickness reduction of the final packaged MEMS components. REFERENCES [1] Fischer, A.C., Forsberg, F., Lapisa, M., Bleiker, S.J., Stemme, G., Roxhed, N. and Niklaus, F., 2015. Integrating mems and ics. Microsystems & Nanoengineering, 1(1), pp.1-16.[2] Lapisa, M., Stemme, G. and Niklaus, F., 2011. Wafer-level heterogeneous integration for MOEMS, MEMS, and NEMS. IEEE Journal of Selected Topics in Quantum Electronics, 17(3), pp.629-644.[3] Jo, G., Edinger, P., Bleiker, S.J., Wang, X., Takabayashi, A.Y., Sattari, H., Quack, N., Jezzini, M., Lee, J.S., Verheyen, P. and Zand, I., 2022. Wafer-level hermetically sealed silicon photonic MEMS. Photonics Research, 10(2), pp.A14-A21.[4] Edinger, P., Jo, G., Van Nguyen, C.P., Takabayashi, A.Y., Errando-Herranz, C., Antony, C., Talli, G., Verheyen, P., Khan, U., Bleiker, S.J. and Bogaerts, W., 2023. Vacuum-sealed silicon photonic MEMS tunable ring resonator with an independent control over coupling and phase. Optics Express, 31(4), pp.6540-6551.[5] Wang, X., Bleiker, S.J., Edinger, P., Errando-Herranz, C., Roxhed, N., Stemme, G., Gylfason, K.B. and Niklaus, F., 2019. Wafer-level vacuum sealing by transfer bonding of silicon caps for small footprint and ultra-thin MEMS packages. Journal of microelectromechanical systems, 28(3), pp.460-471. Figure 1

(Invited) Optical Biosensors in Photonic Integrated Circuits for Smart System Integration

Photonic integrated circuits (PIC) are like electronic integrated circuits drivers of communication systems. Moreover, state-of-the-art technologies enable the fabrication of electronic-photonic integrated circuits (ePIC), which allows for example the cointegration of ultra-fast BiCMOS devices with high speed photo detectors. Besides that, this technology provides an attractive platform for biosensors. They open the door for label-free detection of various analytes with high specificity and in real-time. This gives perspective to highly scalable and cost effective technologies for smart system integration of biosensors and electronic readouts to realize a true lab-on-a-chip application.We present the integration of optical biosensors in a Si-based PIC-technology. This comprises a front-end of line with optical waveguides, an integrated Ge-photodiode and a complete back-end of line consisting of three thin and two thick aluminum metal layers. The optical biosensor is integrated by opening the optical waveguide from the backside of the chip. In particular, we released a Si-based slot waveguide, which provides an enhanced evanescent field to interact with the analyte and hence to increase the sensitivity. The slot waveguide is incorporated in a ring resonator and we analyzed the wafer-level performance using the full width at half maximum, which allows us to assess the optical losses. Thermal sensing in a wide temperature range is investigated. In addition, a simple and cost-effective microfluidic is realized and we show initial results of the surface functionalization. Our work demonstrates the compatibility of a photonic biosensor with a photonic integrated circuit technology without any restriction to the standard FEOL and BEOL processing on the wafer front-side, while it keeps the inherent high sensitivity of evanescent-field sensing and opens a route towards smart system integration. Figure 1

Fabrication of a self-aligned multi-waveguide-layer passive Si3N4/SiO2 photonic integrated circuit for a 3-D optical phased array device

Most traditional PICs (photonics integrated circuits) are based on a single-waveguide-layer configuration, which takes advantage of the mature fabrication process from the EIC (electronic integrated circuits) industry; but in the meantime, this configuration also limits the performance of PICs in applications such as OPA (optical phased array) devices. We have proposed a multi-waveguide-layer 3-D (3 dimensional) OPA device and demonstrated its unique advantage in broadband high efficiency. In this paper, we present the fabrication process of the proposed 3-D OPA in detail. By developing the fabrication process with a single lithography step, we address the two potential issues in a multi-waveguide-layer PIC: the alignment between layers; and the accurate spacing control between layers. The detailed considerations of processes are also elaborated, especially in the PR (photoresist) exposure and etching.

US – China trade war: economic and legal aftermaths

The China-US trade war, which was the result of differences in the production structure of the two countries, systemic contradictions in foreign economic policy principles and the struggle for global leadership, has a significant impact on global trade flows and market conditions. The article aims to identify the key beneficiaries of the trade war, to assess the situation in individual industry markets, as well as global legal effects, which remain out of academic discourse. US pharmaceutical companies and manufacturers of electronic integrated circuits, diodes, transistors, semiconductors and other high-tech components are the main beneficiaries of the trade war, while US consumers are facing rising import prices. Chile, Malaysia, Argentina, Brazil, Canada are external beneficiaries due to the growth in the supply of agricultural products and metals. Malaysia, Vietnam, Taiwan, Hong Kong, Singapore, South Korea and Japan win in electronics, while Vietnam, Pakistan, Bangladesh, Sri Lanka, Cambodia, as well as India get additional advantages in textile production. The United States aimed at ousting China from the world rare earth metals market, forming an investment coalition consisting of Australia and Japan. The systemic spread of sanctions and trade restrictions is shifting the trade disputes resolution from the global level towards the US legal system, which seems to be relatively more efficient in resolving trade disputes.

DNA-based programmable gate arrays for general-purpose DNA computing.

The past decades have witnessed the evolution of electronic and photonic integrated circuits, from application specific to programmable1,2. Although liquid-phase DNA circuitry holds the potential for massive parallelism in the encoding and execution of algorithms3,4, the development of general-purpose DNA integrated circuits (DICs) has yet to be explored. Here we demonstrate a DIC system by integration of multilayer DNA-based programmable gate arrays (DPGAs). We find that the use of generic single-stranded oligonucleotides as a uniform transmission signal can reliably integrate large-scale DICs with minimal leakage and high fidelity for general-purpose computing. Reconfiguration of a single DPGA with 24 addressable dual-rail gates can be programmed with wiring instructions to implement over 100 billion distinct circuits. Furthermore, to control the intrinsically random collision of molecules, we designed DNA origami registers to provide the directionality for asynchronous execution of cascaded DPGAs. We exemplify this by a quadratic equation-solving DIC assembled with three layers of cascade DPGAs comprising 30 logic gates with around 500 DNA strands. We further show that integration of a DPGA with an analog-to-digital converter can classify disease-related microRNAs. The ability to integrate large-scale DPGA networks without apparent signal attenuation marks a key step towards general-purpose DNA computing.

Origin of residual strain in heteroepitaxial films

Heterogeneous integration of diverse materials structures is critical to the scaling of electronic and photonic integrated circuits. For a model system of Ge-on-Si, we experimentally examine the roles of lattice misfit and thermal expansion misfit in determining the residual strain in as-grown and annealed heteroepitaxial films. We present data for Ge-on-Si growth from 400 to 730 °C followed by heat treatment from 500–900 °C. We show that strain fluctuations of 5.02% enable misfit dislocation formation, and we propose a comprehensive model for the conversion of compressive misfit strain to tensile elastic strain. The model is expressed in terms of three regimes: (1) misfit control for the low temperature growth regime at 400 °C; (2) point defect control via annealing in the point defect recovery regime at 500–650 °C; and (3) thermal expansion control for growth or anneal at T > 650 °C in the dislocation recovery regime. Growth from 400 to 730 °C exhibits near complete misfit strain relief by misfit dislocations leaving a consistent residual compressive strain of 0.09%. Growth at 400 °C followed by post growth heat treatment at 600 °C results in vertical threading dislocation density reduction via a point defect-mediated climb mechanism that gives minimal strain relief. Anneal above 650 °C promotes strain relief by dislocation glide. Temperature excursions at T > 730 °C followed by cooling to room temperature yield plastic strain in the Ge film that cannot be further relieved by thermal expansion misfit accommodation. Growth at 400–730 °C retains a residual compressive strain that represents the nucleation threshold for misfit dislocations.

Relative estimation of scattering noise and electronic noise of a radiation detector

This study investigates two unavoidable noise factors: electronic noise (EN) and radiation scattering, associated with detectors and their electronics. This study proposes a novel methodology to estimate electronic and scattering noise separately. It utilizes mathematical tools, namely, Kanpur theorem-1 (KT-1), standard deviation, similarity dice coefficient parameters, and experimental computerized tomography technique. Four types of gamma detectors: CsI (Tl), , NaI (Tl) and HPGe are used with their respective electronics. A detector with integrated circuit electronics imparts significantly less (∼33% less) EN in data than detectors with distributed electronics. KT-1 signature is proposed as a scattering error estimate. The developed empirical expression shows that scattering noise depends strongly on the mass attenuation coefficients of detector crystal material and weakly on their active area. The difference between predicted and estimated relative scattering is 14.6%. The methodology presented in this study will assist the related industry in selecting the appropriate detector of optimal diameter, thickness, material composition and hardware as per requirement.