Electronic Design Automation Software Research Articles

A Bridged Contactless Measurement Technique for LC Tank Based Voltage-Controlled Oscillator

This paper presents a bridged contactless measurement technique that can measure the resonant frequency and quality factor of a fully-integrated powered off voltage-controlled oscillator (VCO). Unlike the use of the conventional two-coil inductive link, the proposed technique uses an additional inductor to bridge the coupling between the LC tank and the external inductor serving measurement purposes. This makes it possible to examine the on-chip high frequency oscillator with an off-chip inductor at Printed Circuit Board (PCB) level. As an example, a K-band VCO as well as the proposed test structure have been designed and simulated using 0.13 μm CMOS technology. The quality factor and operating frequency of the oscillator are measured using the proposed contactless technique through extraction from the frequency response of a bridged inductive link. The efficiency of the method has been validated by full wave electromagnetic simulation. As a reference, the characterization of the oscillator is also obtained using the Cadence Spectre RF and Mentor Graphic's Calibre PEX commercial Electronic Design Automation (EDA) software. The results of these two solutions agree considerably well, which supports the feasibility and potentials of using this technique for contactless measurements.

Multiobjective Bayesian Optimization for Active Load Modulation in a Broadband 20-W GaN Doherty Power Amplifier Design

This paper proposes a multiobjective Bayesian optimization strategy to deal with the complex matching problem of designing a broadband 20-W gallium nitride Doherty power amplifier (DPA). Applying the proposed method, the DPA’s matching networks are optimized to align the desired and the realized impedance trajectories both at saturation and power backoff from 1.5 to 2.4 GHz. By combining a programming environment with the commercial electronic design automation (EDA) software, the optimization process is implemented automatically. Comparison designs reveal that the proposed method outperforms the built-in optimizer of the commercial EDA software for broadband DPA designs. When tested with a single-carrier 20 MHz long-term evolution signal, the measured results show that the DPA achieves an average efficiency of 45.3%–53.6% at 7 dB backoff across the band, with the adjacent channel power ratio levels better than −45.6 dBc after using digital predistortion.

HDL-Based Synthesis System with Debugger for Current-Mode FPAA

The study demonstrates original environment for synthesizing and implementing current-mode analog circuits in the field programmable analog array (FPAA) technology. The described approach is inspired by existing solutions for digital circuits, implemented using a field programmable gate array. The tools are compatible with the existing hardware architecture description standards (VHDL-AMS, HSPICE) and the existing electronic design automation software. The functionality of the system was divided into a synthesis stage (independent on the hardware layer) and an implementation stage (dedicated to an FPAA platform chosen by the user). This article presents parasitics oriented place&route algorithms of the original system and a method for calibrating the analog part. The tools are also equipped with the option of debugging a programmed circuit. The author presents the functionality of the system with an example of an implementation of a 5th order filter pair and a 35–18–26 perceptron with a balanced structure. The summary is an analysis of the complexity of the implemented algorithms and the measurement of program run-times.

Design of Automatic Identification System (AIS) Receiver for Low Earth Orbit (LEO) Satellite

The vessel monitoring system at the sea with Automatic Identification System (AIS) technology will be more effective if AIS receivers are put on satellites because the satellite’s coverage can extend to thousands of kilometers when orbiting in the space. The process of receiving AIS signals in the space has a problem of low received power reaching -102.07 dBm. This value comes from the link budget calculation. This paper offers the design and simulation of a CubeSat AIS receiver payload that can operate to receive AIS signals in the orbit at the altitude of 650 km. The AIS receiver is designed to run at 161.975 MHz and 162.025 MHz using Gaussian Minimum Shift Keying (GMSK) modulation method. In this work, the AIS receiver is designed using radio frequency (RF) module Si4362 with operating temperature of -40° to +85° Celsius suitable for the space environment. Here, AIS signal modulation and demodulation methods were simulated using an electronic design automation software for radio frequency components. The simulation results showed the AIS receiver can receive AIS signals under appropriate conditions with link budget calculation. Finally, end-to-end AIS system simulations were carried through real conditions. The results showed the AIS system designed functions at full capacity.

Bayesian Optimization for Broadband High-Efficiency Power Amplifier Designs

This paper proposes a novel, optimization-oriented strategy for the design of broadband, high-efficiency power amplifiers (PAs) using Bayesian optimization (BO). The optimization algorithm optimizes the drain waveforms by maximizing the fundamental output power while minimizing the harmonic and dissipated components. The optimization process is automated using simulation software. Circuit-based BO and electromagnetic-based (EM-based) BO are applied to design 10 and 30 W PAs. The 10 W PA designed using circuit-based BO achieves a drain efficiency higher than 60% with output power greater than 39.8 dBm from 1.5 to 2.5 GHz, while the 30 W PA designed using EM-based BO offers a drain efficiency higher than 57% with output power greater than 43.8 dBm across the band. Upon comparison of results, it is revealed that the proposed strategy outperforms a commercial electronic design automation (EDA) software's built-in optimizer, thus demonstrating that the EM-based BO is well-suited to the challenge of high power designs.

Ionizing radiation effect on metal–ferroelectric–insulator–semiconductor memory capacitors

A theoretical model was developed to investigate the ionizing radiation effect on the electrical characteristics of metal–ferroelectric–insulator–semiconductor (MFIS) structure capacitors under exposure to radiation and under post-irradiation conditions. In this model, the radiation-induced degradation in the ferroelectric layer, oxide layer and silicon dioxide interface were considered, and the radiation effect of the silicon substrate was also taken into account to accommodate the dose rate effect. The modeling results showed that both the capacitance versus applied voltage (C–V) curves and the surface potential versus applied voltage (ΦS(Si)–V) curves shifted significantly and the memory window became worse with increasing total dose. Moreover, the derived results indicated that the symmetry of the polarization versus applied voltage (P–V) curves degraded with the increase in total dose, which may explain the phenomena of radiation-induced fatigue and imprint. These results can provide some insights into the estimation of the radiation-induced degradation of MFIS structure devices and may be integrated into electronic design automation (EDA) software for ionizing radiation effect simulation.

Modeling of metal-ferroelectric-insulator-semiconductor structure considering the effects of interface traps

An improved model, in which the interface traps effects are considered, is developed by combining with quantum mechanical model, dipole switching theory and silicon physics of metal-oxide-semiconductor structure to describe the electrical properties of metal-ferroelectric-insulator-semiconductor (MFIS) structure. Using the model, the effects of the interface traps on the surface potential ( ϕ Si ) of the semiconductor, the low frequency (LF) capacitance-voltage ( C-V ) characteristics and memory window of MFIS structure are simulated, and the results show that the ϕ Si - V and LF C-V curves are shifted toward the positive-voltage direction and the memory window become worse as the density of the interface trap states increases. This paper is expected to provide some guidance to the design and performance improvement of MFIS structure devices. In addition, the improved model can be integrated into electronic design automation (EDA) software for circuit simulation.

Grand designs, micro scales

ELECTRONICS ENGINEERS engaged in the design of integrated circuits, systems on chip (SoCs), application-specific integrated circuits (ASICs) and other semiconductors face a complex, time-consuming task. It's one that calls for all the help they can get from electronic design automation (EDA) software when it comes to simulating and testing their wares prior to fabrication, and with the constant flow of innovation in the integrated circuit (IC) market, the producers of software design tools are upping their game in order to keep pace.

The correct account of nonzero differential conductance in the saturation regime in the MOSFET compact model

SUMMARYWe suggest a simple and versatile approach for the correct account of differential conductance in the saturation regime that provides a monotonic decrease of the differential conductance from its maximum value to its minimum positive or even negative value. We present all equations also in normalized form, which simplifies the analysis and usage of the approach. On the basis of the suggested approach, we have developed ‘internal’ (does not include source and drain resistance) metal–oxide–semiconductor field‐effect transistor compact model and have incorporated one into an Electronic Design Automation software Symica as Verilog‐A module. Copyright © 2014 John Wiley & Sons, Ltd.

Design automation of ΔΣ switched capacitor modulators using spice and MATLAB

Concerning the fact that the design of contemporary integrated circuits (IC) is practically impossible without using sophisticated Electronic Design Automation (EDA) software, this paper gives some interesting thoughts and considerations about that issue. As technology processes advances on year basis consequently EDA industry is forced to follow this trend as well. This, on the other hand, requires IC designer to frequently and efficiently accommodate to new working environments. Authors of this paper suggest a method for high level circuit analysis that is based on using common (open source or low cost) circuit simulators but precise and fast enough to meet requirements imposed by demanding mixed-signal blocks. The paper demonstrates the proposed EDA procedure on an example of second order ?? modulator design. It illustrates considerable simulation time saving which is more than welcome in a world of analogue and mixed-signal design.

Transistor Modeling and TCAD

The semiconductor industry faces two types of complexity. One is associated with generating and managing large amounts of data that define physical layouts. The other is associated with the nonlinear behaviors of semiconductor processes, devices, and circuits. Computer-aided design (CAD) tools help engineers deal with both types of complexity. Electronic design automation (EDA) software handles a range of tasks associated with the generation, verification, and storage of layout data. Physics-based process, device, and circuit simulators predict the behaviors that result from nonlinear phenomena. The apparently natural division of semiconductor CAD software into EDA tools and physics-based simulators of nonlinear phenomena is modified in practice by the fact that EDA tools and circuit simulators are used primarily by circuit designers, and process and device simulators are used primarily by technology developers. The CAD tools used by circuit designers are referred to as “electronics CAD (ECAD),” and the tools used by technology developers are referred to as “technology CAD (TCAD).” This partitioning of physics-based simulators by user communities can cause potentially useful connections between TCAD and circuit simulators to be neglected. These connections are the subject of this article.

Modeling of MFIS-FETs for the Application of Ferroelectric Random Access Memory

It is recognized that the conventional model for metal-ferroelectric-insulator-semiconductor field-effect transistors (MFIS-FETs) always neglects the history-dependent electric field effect of the ferroelectric layer. In this paper, an improved model combining the dipole switching theory with the silicon physics of metal-oxide-semiconductor structures and with Pao and Sah's double integral, respectively, is proposed to describe the capacitance-gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) characteristics of MFIS structures and the drain current-gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) and drain current-drain voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ) characteristics of MFIS-FETs. Close agreement between modeling and experimental results confirms the validity of the improved model. The influence of the gate voltage, SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer thickness, and interface layer thickness on the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> , and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> characteristics are simulated and discussed. The memory windows of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> characteristics, as well as the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> characteristics, increase with increasing gate voltage. The thicker the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> or interface layer, the worse the transistor characteristics. This paper is expected to provide some guidance to the design and performance improvement of MFIS structure devices. In addition, the mathematical description can be easily combined with electronic design automation software for circuit simulation.

Vibration energy harvesting using macro-fiber composites

The decreasing energy consumption of today’s portable electronics has invoked thepossibility of energy harvesting from the ambient environment for self-power supply. Onecommon and simple method for vibration energy harvesting is to utilize the directpiezoelectric effect. Compared to traditional piezoelectric materials such as lead zirconatetitanate (PZT), macro-fiber composites (MFC) are characterized by their flexibility onlarge deformation. However, the energy generated by MFC is still far smallerthan that required by electronics at present. In this paper, a vibration energyharvesting system prototype with MFC patches bonded to a cantilever beam isfabricated and tested. A finite element analysis (FEA) model is established toestimate the output voltage of the MFC harvester. The energy accumulationprocedure in the capacitor is simulated by using the electronic design automation(EDA) software. The simulation results are validated by the experimental ones.Finally, to optimize the efficiency of energy harvesting, the effects of the electricalproperties of MFC as well as the geometric configurations of the cantilever beam andMFC are parametrically studied by combining the FEA and EDA simulations.

A model for the C–V characteristics of the metal–ferroelectric–insulator–semiconductor structure

A model is developed to describe the characteristics of the metal–ferroelectric–insulator–semiconductor (MFIS) structure based on the dipole switching theory (DST) and the silicon physics of metal–oxide–semiconductor (MOS) structure. The ferroelectric dipole distribution function is used to simulate the history-dependent electric field effect of the ferroelectric layer. Using the model, the thickness effects of the ferroelectric and insulator layers on the capacitance–voltage ( C–V) characteristic and the memory window were investigated for Pt/SBT/ZrO 2/Si and Pt/BLT/MgO/Si structures. All the simulation results show good agreement with the experimental results, indicating that the model is suitable for simulating the C–V characteristic and the memory window of MFIS structure. In addition, the mathematical description is simple and can be easily integrated into the electronic design automation (EDA) software for circuit simulation.

EDA toolbox for VHF Data Link system simulation

Commercial communication systems design software is usually shipped with libraries and toolboxes covering standards like GSM or UMTS. For designing aeronautical communication systems such ready-to-use libraries are rare. Low-level elements and functional blocks have to be adopted and used instead. In this paper a toolbox consisting of system elements for the use with electronic design automation software was developed. It enables radiofrequency design engineers to perform system level simulations using specialised components dedicated to aeronautical communication. For this, functional blocks within the physical layer of VHF Data Link were defined and made available. They cover basic radio frequency (RF) baseband operations as well as modulation, demodulation and power-ramp functionality. The library was tested and verified with a VHF Data Link Mode 4 signal generation application as well as with a VHF Data Link Mode 2 system simulation set-up. While the toolbox presented in this paper is intended to speed up development cycles by providing ready-to-use VHF Data Link functional blocks to radiofrequency system engineers, it is also a useful tool in signal generation and receiver testing.

A model for the polarization hysteresis loops of the perovskite-type ferroelectric thin films

A model has been developed for the P-E hysteresis behavior from the perspective of dipole switching. Hysteresis loops have been reproduced with the model to agree reasonably well with the experimental data measured from various ferroelectric thin films. The model can also predict asymmetric hysteresis loop measured under unconventional situation. Additionally, the mathematical description can be easily combined with electronic design automation software in circuit simulation of ferroelectric capacitor or ferroelectric field effect transistor.

Modeling ferroelectric capacitors based on the dipole switching theory

In this paper, we derived a compact model for the description of the P–E hysteresis behavior based on the dipole switching theory. Simulation results show good agreement with the experiment for various hysteresis loops, and the mathematical description can be easily combined with an electronic design automation software for circuit simulation. Therefore, the model can be used for both circuit simulation and providing better intuition for the ferroelectric material behavior.

3GPP W-CDMA systems: design and testing

Newly emerging wireless signal formats can present significant design challenges to the system design engineer. Wideband code division multiple access (W-CDMA) can present many engineering design and verification challenges, due to its physical layer complexity as well as complexities that can arise when integrating RF and baseband designs to achieve a working system. System design engineers typically have the task of interpreting standards specifications, first for partitioning subsystem requirements, then verifying that the end-to-end system design (typically including both baseband and RF designs) will meet specifications when they are finally integrated. This article considers a case study that illustrates the importance of simulating baseband and RF designs together to accomplish this task. Specifically, a conceptual system design that includes system models, a fixed-point finite impulse response filter, and transistor-level circuit design is simulated and verified together against measurements defined in the third-generation partnership project (3GPP) W-CDMA standards specifications. Tradeoffs between improving either the RF or baseband design to meet overall system specifications will be discussed. Finally, design verification using "connected solutions," or connectivity between, electronic design automation software and test equipment will be described, illustrating how verification testing can be started earlier to help reduce risk by identifying performance issues early in the design cycle, when they are potentially easier and costly to implement.

S-domain methods for simultaneous time and frequency characterization of electromagnetic devices

An efficient procedure is developed for simultaneously characterizing the time-domain and frequency-domain behavior of electromagnetic devices. The procedure works in the complex-frequency plane called the s-domain-and provides an analytical expression for the behavior of the device at any frequency and for any transient excitation. This analytical expression is obtained by first evaluating a reduced-order model of the poles and zeros of the device. These poles and zeros are then used to characterize the device in terms of rational polynomials in the s-domain. Two different methods for evaluating reduced-order models are presented. One is called asymptotic waveform evaluation (AWE) and is combined with the finite-element method; the other is called adaptive Lanzcos-Pade sweep (ALPS) and is combined with the boundary-element method. The resulting reduced-order models provide the frequency-domain behavior of the device over a broad bandwidth. Using the Laplace transform, these reduced-order models also provide the time-domain behavior. Several numerical examples have been run using commercial electronic design automation (EDA) software to demonstrate that this solution procedure is a highly efficient and accurate way to characterize the electromagnetic performance of real-life devices.

Undergraduate field applications engineers: a successful experiment in electronic design automation technology transfer

The United States has lost its leadership position in semiconductor manufacturing. It is, however, still dominant in the production of electronic design automation (EDA) software which supports semiconductor integrated circuit design and manufacturing. Research on EDA software is performed primarily in US universities. Early use of such software by the US semiconductor industry should constitute a precompetitive advantage that would help to compensate for the US's tack of competitiveness in manufacturing; however, because of the different natures of universities and industry, a significant technology transfer gap exists between them. Universities produce prototype software as research results, whereas the semiconductor industry would prefer to have robust rather than prototype versions. To bridge the gap, it has been proposed that the EDA industry be emulated and undergraduate engineering students used as field applications engineers (UFAEs). This paper describes a reasonably successful first attempt at this approach to EDA software technology transfer and discusses as well what could be done in the future to improve upon it.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>