Electromigration-induced Failure Research Articles

Insights Into the Grain Orientation Effect on Electromigration-Induced Failure in Solder Interconnects Through Phase Field Modeling

Insights Into the Grain Orientation Effect on Electromigration-Induced Failure in Solder Interconnects Through Phase Field Modeling

Electromigration-induced microstructure evolution and failure mechanism of sintered nano-Ag joint

Nanosized silver (nano-Ag) has been proposed as a flip-chip interconnection material owing to its low sintering temperature and impressive working performance. With ever-shrinking size of electronic devices, electromigration (EM) becomes an important reliability issue. However, the EM behavior of nano-Ag joints has rarely been investigated before. In this study, a flip-chip structured nano-Ag joint was examined at a current density of 1.0 × 104 A/cm2 at 150 °C and its microstructural change at different experimental times was analyzed. Severe delamination between the Cu substrate and sintered Ag occurred at the cathode, and the extent of delamination increased with increasing EM time. Fractured surfaces revealed the presence of a large number of whiskers on the opposite side of the cathode owing to stress release during the EM process. For comparison, a Sn-3Ag-0.5Cu solder joint was examined under identical experimental conditions. Although failure in both samples originated from the cathode, the failure mechanism was different. The root cause for the difference in the EM phenomenon observed in the two types of materials was determined in this study.

Electromigration-induced void evolution and failure of Cu/SiCN hybrid bonds

The realization of high interconnect densities for three-dimensional integration demands development of new wafer-to-wafer bonding approaches. Recently introduced Cu-to-Cu wafer-to-wafer hybrid bonding schemes overcome scaling limitations, but like other Cu-based interconnect structures, they are prone to electromigration. Migration and growth of voids, induced by electromigration and mechanical stress, cause Cu-to-Cu hybrid bonds to fail. A comprehensive modeling approach is required to fully understand the complex dynamics of voids with their influencing factors, such as current density, temperature, and mechanical stress. In this work, we utilize such a modeling approach to perform studies of void migration through Cu-to-Cu hybrid bonds. The calculated velocities of the evolving void surface fully correspond to the experimentally observed behavior of voids migrating from the lower pad to the upper diffusion barrier of the upper pad, where they cause electrical failure. The migration velocity of a void in the upper pad is 20% higher than the migration velocity of a void in the bottom pad. Unbalance of the normal velocity distribution at the void surface leads to the transformation of the originally ellipsoid void into a teardrop shape. The simulations provide full insight in the impact of layout geometry, material properties, and operating conditions on void dynamics. In addition, the results enable targeted adjustments of the influencing factors to inhibit void migration and growth in order to delay or to fully prevent Cu-to-Cu hybrid bond failure.

Electromigration Reliability of Advanced High-Density Fan-Out Packaging With Fine-Pitch 2-/2-μm L/S Cu Redistribution Lines

The novel fan-out (FO) packaging incorporating fine-pitch small linewidth Cu redistribution line (RDL) technology was designed for achieving high-density packaging. However, the downsizing of Cu RDLs gives rise to increasing current densities and raises the electromigration reliability concerns. The failure mechanism involved under electromigration in the advanced fine-pitch package still remains unclear at the present stage. This article investigated the electromigration reliability and the failure mechanism of an advanced FO packaging with fine-pitch 2-/2- $\mu \text{m}$ line/spacing Cu RDLs, $3~\mu \text{m}$ in thickness and 20 or $600~\mu \text{m}$ in length, embedded in polyimide dielectric layers. The Cu RDLs were stressed with the electric current at $8.8\times 10^{5}$ A/cm2 under an ambient 180 °C. The geometry effects of the Cu RDL on the electromigration performance were also elaborated, and the design rule was proposed for reliability optimization. The Cu RDL incorporating a bent-line (45°) structure was found to exhibit a better electromigration resistance compared with the one incorporating a straight-line structure. The in situ resistance analysis revealed a steady resistance increase followed by a rapid resistance jump until open-circuit failure for both 20- and 600- $\mu \text{m}$ -long Cu RDLs. The fracture microstructures further revealed the failure occurrence in the middle region of the Cu RDL rather than on the cathode side, showing atypical failure mechanism under electromigration. The local heat accumulation in the middle region of the Cu RDL produced a large thermal gradient and further triggered Cu thermomigration, which were responsible for the electromigration-induced failure in the fine-pitch Cu RDLs.

Making a Case for Partially Connected 3D NoC

3D Network-on-Chip (3D NoC) enables design of high-performance and energy-efficient manycore computing platforms. Two of the commonly used vertical interconnection technologies are: through silicon via (TSV) and near-field inductive coupling (NFIC). Both TSV- and NFIC-based links introduce additional area overhead. One of the possible ways to reduce the area overhead is to design partially connected 3D NoC with minimal effect on overall performance. The achievable performance of the partially connected 3D NoCs depends on the area, energy, and bandwidth of the vertical links. Moreover, the electromigration-induced failure of TSV is more severe than the misalignment-induced error in NFIC. By considering all these pertinent factors, we demonstrate that it is indeed possible to design a partially connected NFIC-based 3D NoC that performs as good as a fully connected TSV-based counterpart when the data rate is below a certain limit. For higher data rates, the partially connected TSV-based 3D NoC is a viable solution. However, NFIC-based 3D NoC is always more robust than the TSV-based counterpart.

Modeling Effect of Grain Orientation on Degradation in Tin-Based Solder—Part II: Electromigration Experiments

In a series of articles, we consider the effects of the microstructure and the associated anisotropy of Sn grains on electromigration in lead-free solder bumps. In this article, we carried out experiments to characterize microstructures of tin-based solder bumps and to investigate their effects on electromigration-induced failure. Accelerated electromigration tests and electron backscatter diffraction (EBSD) tests are performed on tin-based solder bumps in wafer-level chip-scale packages (WLCSPs). EBSD analysis, together with the results of time to failure from accelerated electromigration tests, provides valuable information on the effects of the microstructure on electromigration-induced failure that can be used for predictive modeling. For Ni-based metallization, we find that tin self-diffusion is the dominant degradation mechanism and a strong effect of the grain orientation in the solder on the time to failure.

Effect of Cu solubility on electromigration in Sn(Cu) micro joint

The present work investigated the effect of in-situ Cu solubility on electromigration behavior in the current-stressed Cu/Sn/Cu microjoint. Firstly, we deduced that the in-situ Cu solubility in a current-stressed Cu/Sn/Cu microjoint can be determined by the magnitude relationship between the dissolution Cu flux and the electromigration Cu flux in the current-stressed Sn matrix. And, the in-situ Cu solubility in the current-stressed Sn solder matrix governs the electromigration-induced failure modes of the microCu/Sn/Cu solder joints. If the dissolution Cu flux is larger than the electromigration Cu flux, the equilibrium Cu solubility can be maintained in the Sn solder matrix, and the electromigration of the Sn host atoms can be retarded. Thus, no electromigration-induced voids could occur in the Sn solder matrix. Only electromigration-induced Cu-pad consumption could be observed at the cathode Sn/Cu interface under this condition. On the other hand, if the dissolution Cu flux is smaller than the electromigration Cu flux, the Cu solute in the Sn matrix phase is depleted by the electromigration Cu flux. Then, the Sn host atoms would electromigrate toward the anode side. Void formation occurs in the Sn matrix phase near the cathode interface.Using the magnitude relationship between the dissolution Cu flux and the electromigration Cu flux, the boundary parameters (critical temperatures and current densities) defining the electromigration-induced failure modes can be obtained. With the obtained boundary parameters, an electromigration-induced failure diagram is constructed, which can distinguish and predict the electromigration-induced failure modes (void formation and Cu-pad consumption) in the microCu/Sn/Cu solder joint.

A theoretical analysis to current exponent variation regularity and electromigration-induced failure

The electric current exponent, typically with j−n form, is a key parameter to predict electromigration-induced failure lifetime. It is experimentally observed that the current exponent depends on different damage mechanisms. In the current research, the physical mechanisms including void initiation, void growth, and joule heating effect are all taken into account to investigate the current exponent variation regularity. Furthermore, a physically based model to predict the mean time to failure is developed and the traditional Black's equation is improved with clear physical meaning. It is found that the solution to the resulting void initiation and growth equation yields a current exponent of 2 and 1, respectively. On the other hand, joule heating plays an important role in failure time prediction and will induce the current exponent n > 2 based on the traditional semi-empirical model. The predictions are in agreement with the experimental results.

Dominant effect of high anisotropy in β-Sn grain on electromigration-induced failure mechanism in Sn-3.0Ag-0.5Cu interconnect

The effect of high diffusivity anisotropy in β-Sn grain on electromigration behavior of micro-bumps was clearly demonstrated using Sn-3.0Ag-0.5Cu solder interconnects with only two β-Sn grains. The orientation of β-Sn grain (θ is defined as the angle between the c-axis of β-Sn grain and the electron flow direction) is becoming the most crucial factor to dominate the different electromigration-induced failure modes: 1) the excessive dissolution of the cathode Cu, blocking at the grain boundary and massive precipitation of columnar Cu6Sn5 intermetallic compounds (IMCs) in the small angle θ β-Sn grain occur when electrons flow from a small angle θ β-Sn grain to a large one; 2) void formation and propagation occur at the cathode IMC/solder interface and no Cu6Sn5 IMCs precipitate within the large angle θ β-Sn grain when electrons flow in the opposite direction. The EM-induced failure mechanism of the two β-Sn grain solder interconnects is well explained in viewpoint of atomic diffusion flux in β-Sn.

Phase segregation, interfacial intermetallic growth and electromigration-induced failure in Cu/In–48Sn/Cu solder interconnects under current stressing

The evolution of microstructure in Cu/In–48Sn/Cu solder bump interconnects at a current density of 0.7 × 104 A/cm2 and ambient temperature of 55 °C has been investigated. During electromigration, tin (Sn) atoms migrated from cathode to anode, while indium (In) atoms migrated from anode to cathode. As a result, the segregation of the Sn-rich phase and the In-rich phase occurred. A Sn-rich layer and an In-rich layer were formed at the anode and the cathode, respectively. The accumulation rate of the Sn-rich layer was 1.98 × 10−9 cm/s. The atomic flux of Sn was calculated to be approximately 1.83 × 1013 atoms/cm2s. The product of the diffusivity and the effective charge number of Sn was determined to be approximately 3.13 × 10−10 cm2/s. The In–48Sn/Cu IMC showed a two layer structure of Cu6(Sn,In)5, adjacent to the Cu, and Cu(In,Sn)2, adjacent to the solder. Both the cathode IMC and the anode IMC thickened with increasing electromigration time. The IMC evolution during electromigration was strongly influenced by the migration of Cu atoms from cathode to anode and the accumulation of Sn-rich and In-rich layers. During electromigration, the Cu(In,Sn)2 at the cathode interface thickened significantly, with a spalling characteristic, due to the accumulation of In-rich layer and the migration of Cu atoms - while the Cu(In,Sn)2 at the anode interface reduced obviously, due to the accumulation of Sn-rich layer. The mechanism of electromigration-induced failure in Cu/In–48Sn/Cu interconnects was the cathode Cu dissolution-induced solder melt, which led to the rapid consumption of Cu in the cathode pad during liquid-state electromigration and this finally led to the failure.

Electromigration-induced failure in operando characterization of 3D interconnects: microstructure influence

An accurate knowledge of the phenomenon is required to develop a predictive modeling of the electromigration failure. Thus, a hitherto unseen SEM in operando observation method is devised. The test structure with “high density” through silicon vias (TSV) is tested at 623K with an injected current density of 1MA/cm2. Regular shots of micrographs inform about the voids nucleation, forced in copper lines above the TSV, and about the scenario of their evolution. A clear relation is established between voids evolution and the one of the electrical resistance. The lack of impact of test conditions on the failure mechanism is demonstrated. Finally, the impact of microstructure on the depletion mechanism is discussed. Grain boundaries are preferential voids nucleation sites and influence the voids evolution. A probable effect of grain size and crystallographic orientation is revealed.

Architecture implications of pads as a scarce resource

Due to non-ideal technology scaling, delivering a stable supply voltage is increasingly challenging. Furthermore, com- petition for limited chip interface resources (i.e., C4 pads) between power supply and I/O, and the loss of such resources to electromigration, means that constructing a power deliverynetwork (PDN) that satisfies noise margins without compromising performance is and will remain a critical problem for architects and circuit designers alike. Simple guardbanding will no longer work, as the consequent performance penalty will grow with technology scaling In this paper, we develop a pre-RTL PDN model, VoltSpot, for the purpose of studying the performance and noise tradeoffs among power supply and I/O pad allocation, the effectiveness of noise mitigation techniques, and the consequent implications of electromigration-induced PDN pad failure. Our simulations demonstrate that, despite their integral role in the PDN, power/ground pads can be aggressively reduced (by conversion into I/O pads) to their electromigration limit with minimal performance impact from extra voltage noise - provided the system implements a suitable noise-mitigation strategy. The key observation is that even though reducing power/ground pads significantly increases the number of voltage emergencies, the average noise amplitude increase is small. Overall, we can triple I/O bandwidth while maintaining target lifetimes and incurring only 1.5% slowdown

Joule-Heating-Induced Damage in Cu-Al Wedge Bonds Under Current Stressing

Copper wires are increasingly used to replace gold wires in wire-bonding technology owing to their better electrical properties and lower cost. However, not many studies have been conducted on electromigration-induced failure of Cu wedge bonds on Al metallization. In this study, we investigated the failure mechanism of Cu-Al wedge bonds under high current stressing from 4 × 104 A/cm2 to 1 × 105 A/cm2 at ambient temperature of 175°C. The resistance evolution of samples during current stressing and the microstructure of the joint interface between the Cu wire and Al-Si bond pad were examined. The results showed that abnormal crack formation accompanying significant intermetallic compound growth was observed at the second joint of the samples, regardless of the direction of electric current for both current densities of 4 × 104 A/cm2 and 8 × 104 A/cm2. We propose that this abnormal crack formation at the second joint is mainly due to the higher temperature induced by the greater Joule heating at the second joint for the same current stressing, because of its smaller bonded area compared with the first joint. The corresponding fluxes induced by the electric current and chemical potential difference between Cu and Al were calculated and compared to explain the failure mechanism. For current density of 1 × 105 A/cm2, the Cu wire melted within 0.5 h owing to serious Joule heating.

A Canary Design to Monitor Electromigration of Solder Joints

Electromigration-induced failure has become one of the most serious problems in solder joints. In this paper, a canary device has been designed to monitor the eletromigration of solder joints. Then the current of the canary device is calculated. The canary solder joints are identical to those used in the host circuit but suffered properly larger environmental stress to accelerate aging so they are supposed to fail before those in the host circuit. For this reason the canary device are designed to be sacrificial, and are not used in the circuit. Instead it is packaged separately in order not to influence the normal operation of the host circuit. How to apply sufficient, but not overly large, stress current to the canary device to enhance its electromigration failure without stressing other part of the circuit becomes one of the problems we need to solve. In this paper a canary circuit is designed to solve this problem. Also the increased stress we need was calculated. With the help of the canary device�E we can be warned before the solder joints fail to ensure the system health.

Electromigration induced failure on lead-free micro bumps in three-dimensional integrated circuits packaging

We report electromigration induced failure on lead-free micro bumps in three-dimensional integrated circuits samples with chip on chip configuration. Compared to flip chip solder joints, micro bumps of chip-on-chip samples exhibit better electromigration resistance and are able to withstand a higher current density. No exhibited electromigration-induced failure was observed when current density was below 2 × 104 A/cm2. A threshold current density to trigger electromigration in chip-on-chip samples was found to be 3.43 × 104 A/cm2. When current density was higher than 7.5 × 104 A/cm2 at an ambient temperature of 150 °C, no void propagation through whole bump opening was found; instead, electromigration induced voids were observed at the cathode side of Al trace.

Current density redistribution from no current crowding to current crowding in Pb-free solder joints with an extremely thick Cu layer

In order to remove the effect of current crowding on electromigration, thick Cu under-bump metallization has been widely adopted in the electronics industry. Three-dimensional (3-D) integrated circuits, using through Si via Cu column interconnects, is being developed, and it seems that current crowding may not be a reliability issue. However, statistical experiments and 3-D finite element simulation indicate that there is a transition from no current crowding to current crowding, caused by void growth at the cathode. An analysis of the electromigration-induced failure mechanism in solder joints having a very thick Cu layer is presented. It is a unique failure mechanism, different from that in flip chip technology. Moreover, the study of marker displacement shows two different stages of drift velocity, which clearly demonstrates the back-stress effect and the development of compressive stress.

Nano- and micrometer-scale thin-film-interconnection failure theory and simulation and metallization lifetime prediction, Part 2: Polycrystalline-line degradation and bulk failure

The degradation and bulk failure of a polycrystalline interconnect line caused by vacancy electromigration along grain boundaries and vacancy-cluster nucleation at triple points in the bulk conductor are investigated within the general theory of the electromigration-induced degradation and failure of thin-film on-chip interconnect lines, presented in Part 1 [1]. The general equations are tailored to deal with vacancy electromigration, mechanical-stress generation, and void nucleation at triple points. Appropriate boundaryvalue problems are formulated, and numerical methods and procedures to solve them are developed and implemented in software. Computer simulations are performed to identify a pattern of electromigration failure at triple points. On this basis, (1) interconnect lifetime is investigated over wide ranges of variation of material, structural, geometric, and operating parameters, and (2) the current-density and temperature dependence—of the mechanical stress, vacancy concentration, and level of vacancy supersaturation at a triple point, and of void radius and time to nucleation-is examined and explained. The simulation results are found to agree well with previous experiments. This investigation could be seen as a natural continuation of our study of electromigration failures developed by multilevel-metallization systems as a result of interconnect failure near via junctions or at open ends [1]. Together they cover most mechanisms of electromigration failure suffered by metallization systems.

Nano- and micrometer-scale thin-film-interconnection failure theory and simulation and metallization lifetime prediction, Part 1: A general theory of vacancy transport, mechanical-stress generation, and void nucleation under electromigration in relation to multilevel-metallization degeneration and failure

The physical principles are considered of on-chip interconnection degeneration and failure in sub-1-µm technologies from the viewpoint of multilevel-metallization reliability. A general theory and simulation results are presented that deal with electromigration-induced failure of thin-film conducting tracks on the micro- and nanometer scales. They provide a detailed treatment of micro-, meso-, and nanoscopic mechanisms underlying the deformation and breaking of actual interconnection configurations. Parts 1 and 2 contain (i) the derivation and analysis of basic kinetic equations; (ii) the formulation and solution of three-dimensional boundary-value problems representing the transport of vacancies (both in the bulk and along grain boundaries) and the development of deformation and stress; (iii) models of void nucleation and development; (iv) an analysis of a multilevel-metallization lifetime; and (v) the identification of potential break locations in a multilevel metallization in relation to current density, metallization structure and layout, temperature, and the grain structure of the conducting material. Part 3 deals with electromigration in doped on-chip polycrystalline interconnections in terms of lengthening their lifetime. To predict electromigration resistance, models are constructed that represent the influence of texture and other grain-boundary properties on the effective charges of native and dopant ions.

The Effect of Microstructure on Electromigration-Induced Failure Development

The effect of the microstructure on the electromigration failure development is analyzed. We investigate the influence of the statistical distribution of copper grain sizes on the electromigration time to failure distribution. Also, the effect of the microstructure on the formation and development of an electromigration-induced void is studied by simulation and the results are compared with experiments. It is shown that the lognormal distribution of the grain sizes resulted in lognormal distributions of the electromigration lifetimes. A close investigation has shown that the network of grain boundaries has a decisive impact in the determination of void nucleation sites and main features of void development.

Electromigration-Induced Failure of Ni/Cu Bilayer Bond Pads Joined with Sn(Cu) Solders

The effect of electromigration (EM) on Sn(Cu)/Ni/Cu solder joint interfaces under current stressing of 104 A/cm2 at 160°C was studied. In the pure Sn/Ni/Cu case, the interfacial compound layer was mainly the Cu6Sn5 compound phase, which suffered serious EM-induced dissolution, eventually resulting in serious Cu-pad consumption. In the Sn-0.7Cu case, a (Cu,Ni)6Sn5 interfacial compound layer formed at the joint interface, which showed a strong resistance to EM-induced dissolution. Thus, there was no serious consumption of the Cu pad under current stressing. In the Sn-3.0Cu case, we believe that the␣massive Cu6Sn5 phase in the solder matrix eased possible EM-induced dissolution at the interfacial compound layer due to current stressing.