Electromigration Failure Time Research Articles

Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study.

To meet the demands for miniaturization and multi-functional and high-performance electronics applications, the semiconductor industry has shifted its packaging approach to multi-chip vertical stacking. Among the advanced packaging technologies for high-density interconnects, the most persistent factor affecting their reliability is the electromigration (EM) problem on the micro-bump. The operating temperature and the operating current density are the main factors affecting the EM phenomenon. Therefore, when a micro-bump structure is in the electrothermal environment, the EM failure mechanism of the high-density integrated packaging structure must be studied. To investigate the relationship between loading conditions and EM failure time in micro-bump structures, this study established an equivalent model of the vertical stacking structure of fan-out wafer-level packages. Then, the electrothermal interaction theory was used to carry out numerical simulations in an electrothermal environment. Finally, the MTTF equation was invoked, with Sn63Pb37 as the bump material, and the relationship between the operating environment and EM lifetime was investigated. The results showed that the current aggregation was the location where the bump structure was most susceptible to EM failure. The accelerating effect of the temperature on the EM failure time was more obvious at a current density of 3.5 A/cm2, which was 27.51% shorter than 4.5 A/cm2 at the same temperature difference. When the current density exceeded 4.5 A/cm2, the change in the failure time was not obvious, and the maximum critical value of the micro-bump failure was 4 A/cm2~4.5 A/cm2.

Electromigration of Plasma Etched Copper Lines of Various Widths and Lengths

Copper (Cu) interconnect lines are widely used in advanced, high-density ICs. Compared with aluminum (Al), Cu has many advantages, such as the higher conductivity and longer lifetime. However, Cu is difficult to etch into fine lines using the plasma etching method because the reaction product is nonvolatile. Another problem of Cu interconnect is that it has poor adhesion to the dielectric film unless an adhesion layer is used. Recently, Kuo’s group solved the etching problem with a novel room-temperature process that consumes the patterned Cu thin film with a plasma reaction and then removes the reaction product with a liquid solution [1,2]. This method has been used in the fabrication of ICs and TFT LCDs [3]. One of the most critical issues in applying Cu lines in products is the reliability - lifetime prediction, which is usually done by the electromigration (EM) measurement [4]. Previously, the Kuo’s group has studied temperature and mechanical bending effects on the Cu fine line’s lifetime [5,6]. However, there are few studies on the geometry effects of the Cu line on the lifetime. In the paper, authors investigated the relationship between the width or length of the Cu line and the EM lifetime. The TiW (10 nm)/Cu (200 nm) thin film stack was sputter deposited on a Corning glass. The TiW film was deposition at 5 mTorr in Ar at 75 W for 15 minutes. The Cu film was deposited at 10 mTorr in Ar at 80W for 60 minutes. The Cu film was patterned with a lithography process using a line-and-space mask. Then, the sample was exposed to a Cl2 /CF4 plasma in the PlasmaTherm 700C system operated in the RIE mode at room temperature. The condition was Cl2/CF4 10/5 sccm at 50 mTorr, 600 W for 3 minutes, corresponding to -VDC = 237 V [7]. After the RIE reaction, the sample was dipped in the 10:1 diluted HCl solution to dissolve the CuClx reaction product. Then, the underneath TiW was RIE etched with CF4 5 sccm at 40 mTorr, 600W for 2 minutes corresponding to -VDC = 273V. The failure time was determined by stressing a sample with the constant current density at room temperature until the current suddenly jumped by several orders of magnitude. Relationships between the line width or length and the EM failure time at different current densities were measured, as shown in Figures 1 and 2, where “L” means the line length and “W” means the line width. Several conclusions can be summarized from these figures. First, the line failure time is shortened with the increase of the current density. Second, under the same current density, the narrow line has a longer lifetime than the wide line. Third, the influence of the line length to the failure time is highly dependent on the line width. In Fig. 1, for 30 µ wide lines, the 800 µ long line has a slightly longer lifetime than that of the 400 µ long line. However, in Fig. 2, for 10 µ wide lines, the 20 µ long line has a lifetime slightly longer than that of the 200 µ long line at the current density of 2.5x106 A/cm2. Separately, for the same 20 µ line length, the lifetime of the 3 µ wide line is longer than that of the 10 µ wide line. For all 10 µ wide lines, the lifetime appears to be longer with the shortening of the line length. The further study on the Cu line width and length effect for narrow Cu lines, i.e., less than 3 µ, is in progress of which the result will be reported. In addition, the breakdown of the Cu line may be related to the edge roughness or the TiW/Cu interface quality, which will also be clarified and reported. Authors acknowledge to support of this work through the NSF CMMI 1633580 project. 1. Y. Kuo and S. Lee, Jpn. J. Appl. Phys. 39(3AB), L188-L190 (2000). 2. Y. Kuo and S. Lee, Appl. Phys. Lett., 78(7), 1002-1004 (2001). 3. Y. Kuo, invited, Proc. 16th Intl. Workshop on Active-Matrix Flat Panel Displays and Devices, 211-214 (2009). 4. J. R. Black, IEEE Reliability Physics Symposium, 142-149 (1974). 5. G. Liu and Y. Kuo, Electrochem. Soc., 156(7), H579-H584. (2009). 6. C. C. Lin and Y. Kuo., Journal of Applied Physics 111(6), 265-10130 (2012). 7. S. Lee and Y. Kuo, Electrochem. Soc., 148(9), G524-G529 (2001). Figure 1

SiO2-coated Cu nanoparticle/epoxy resin composite and its application in the chip packaging field

A silicon dioxide–copper (SiO2-Cu) epoxy resin composite material for chip packaging was made by a mechanical mixing method with epoxy resin as the base glue and SiO2 coated with nano-Cu (SiO2-Cu) particles as the filler. The dispersion of SiO2-Cu nanoparticles in epoxy resin was studied using scanning electron microscopy and transmission electron microscopy. Meanwhile, the effects of the filler on the coefficient of thermal conductivity, the coefficient of thermal expansion (CTE), and the mechanical properties of the composite material were also studied. The results show that SiO2-Cu nanoparticles disperse well in the epoxy resin, the coefficient of thermal conductivity of SiO2-Cu epoxy resin composites increases with an increase in the SiO2-Cu filler amount, the coefficient of thermal conductivity begins to decline when the filling volume is over 25%, and the suitable amount of SiO2-Cu is 25% of the total volume. With the increase in the filler, the CTE of the composite decreases; when the SiO2-Cu filling amount is 25%, the material has good impact resistance and a long electromigration failure time for chip packaging materials.

Plasma-Based Copper Etch Process and Reliability

Copper is widely used as the interconnect material in ultra-large-scale-integrated circuits. The sputter deposition process effects on the copper thin film’s grain structure and resistivity have been studied. Process effects on copper lines prepared with the plasma-based etch process have also been investigated. The etched line edge roughness follows the grain structure. The lifetime of the copper line with respect to the line width was determined from the electromigration failure time. Under the constant voltage stress condition, the lifetime decreases with the decrease of the line width. The plasma-based process is effective in preparing copper fine lines.

Electromigration behaviors of Ge2Sb2Te5 chalcogenide thin films under DC bias

Electromigration (EM) behaviors of pristine Ge2Sb2Te5 (GST), nitrogen-doped GST (N-GST) and cerium-doped GST (Ce-GST) thin-film strips under DC bias are presented. The mean-time-to-failure (MTTF) analysis based on the Black equation found that the EM failure times at room temperature are 1.2 × 104, 40 and 9.2 × 102 years and the activation energies (Ea) of EM process are 1.07, 0.57 and 0.68 eV for GST, N-GST and Ce-GST, respectively. Moreover, the calibration of the current density exponent, n, of Black’s equation found n values are close to 2 for all samples, implying the dominance of grain boundary diffusion during the mass transport of EM process. For doped GSTs, the inferior EM failure lifespans and smaller Ea values were ascribed to the grain refinement effect which increases the number of grain boundaries in such samples. It consequently promoted the short-circuit diffusion and accelerated the EM failure in doped GSTs. The Blech-type tests on GSTs found that the threshold product, i.e., the product of current density and sample length ((j ⋅ L)th), is 200 A/cm for GST, 50 A/cm for N-GST and 66.67 A/cm for Ce-GST. Moreover, the product of diffusivity and effective charge number (i.e., DZ*) for GST, N-GST and Ce-GST was 2.0 × 10−7, 4.5 × 10−6 and 3.8 × 10−6 cm2/sec, respectively. Analytical results illustrated that the electrostatic force effect dominates the EM failure in samples with short strip lengths while the electron-wind force effect dominates the EM failure in samples with long strip lengths. Doping might alleviate the mass segregation in GST; however, its effect was moderate.

Comparison of H2and NH3Treatments for Copper Interconnects

The surface state, electrical, and reliability characteristics of copper (Cu) interconnects after ammonia (NH3) or hydrogen (H2) plasma treatment were investigated in this study. The experimental results show that H2plasma treatment has excellent Cu oxide removal efficiency, less impact on the formation of Cu hillocks, and less damage on low-dielectric constant (low-k) dielectrics in comparison to NH3plasma treatment. However, H2plasma treatment results in a higher leakage current between the Cu lines and shorter electromigration (EM) failure time due to a weaker adhesion strength at the Cu film interface. On the other hand, NH3plasma treatment without the sufficient treatment time would lead to an increased probability of delamination at the Cu/barrier layer interface since the Cu oxide layer can not be completely removed. As a result, extending NH3plasma treatment time can efficiently reduce the adhesion failure and enlarge EM resistance as well.

Study of electromigration void nucleation time in Cu interconnects with doping elements

This study shows that in Cu interconnects with different doping elements (e.g., Al, Co, Mn) electromigration failure times may be significantly increased because of an incubation time prior to the usual void formation. The presence of a significant incubation time provides a change from the common value of 1 to a value of 2 of the current exponent of Black’s equation, mostly used for lifetime extrapolation at use conditions. Moreover, an increase of the activation energy up to 1.4 eV has been experimentally obtained. This gives additional room for reliability lifetime extension.

Electromigration Characteristics for Electron Down-Flow in Copper Interconnects

In this study, electron down-flow electromigration (EM) behavior of Copper (Cu) interconnects was characterized in terms of the line width and the via number. For a single-via structure, slit-like voiding underneath the via and line-depletion modes were observed. The slit-like voiding mode is a fatal EM failure for the narrow and wide Cu lines with a single-via structure due to a relatively short lifetime. This failure mode can be eliminated by optimizing via clean process or increasing redundant via. The line-depletion can be further distinguished two kinds of failure modes in terms of the voiding location and shows the different line width dependence EM behaviors. For line-depletion failure mode with voiding location away from via, the EM failure time increases with increasing the metal width. On the other hand, the failure times are similar in the wide and narrow metal lines for line-depletion mode with voiding location originating from the edge of the via.

Effect of Si-die dimensions on electromigration failure time of flip-chip solder joints

Electromigration tests were performed for solder joints with various Si dies thickness and area. For the electro-migration in flip-chip solder joints with a 60, 100, 250 and 760 μm thick Si die, it is found that Si-die thickness has profound influence on electro-migration lifetime. The average failure time was 1608.0 h for joints with a 760-μm-thick die when they are stressed by 1.0 A at 100 °C. However, it decreased significantly to 0.6 h for joints with a 60-μm-thick die. According to the temperature measured by infrared microscopy, solder joints with a thinner die has a higher Joule heating effect, which results in a shorter electromigration lifetime. In addition, the die area has a considerable influence on the electromigration failure time. The electromigration failure time decreases as the die area decreases. The average failure time is 1608.0, 28.0, 10.6, 5.0 and 0.3 h for the solder joints with die area of 5350 × 4350 μm 2, 5350 × 3600 μm 2, 5350 × 3000 μm 2, 5350 × 2000 μm 2 and 5350 × 1000 μm 2, respectively. The Joule heating effect becomes more serious in smaller dies, which causes a shorter electromigration lifetime.

The effect of stress migration on electromigration in dual damascene copper interconnects

Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to stress migration (SM) and electromigration (EM). At use condition, these two failure mechanisms play a collective role in causing interconnect failure. We present a study on SM and EM interaction in lower (MX structure) and upper metal (MX+1 structure) of dual-damascene Cu/low-κ interconnects. It is found that both mechanisms are dependent; statistical analysis shows that EM failure time is affected by the presence of residual stress induced by SM. This effect was more severe in the lower metal, where the EM median-time-to-failure (t50) for the majority of samples could be degraded by 30%–60%. For the upper metal of Cu interconnects, the t50 is degraded by about 10%. The reliability implication of the residual stress in copper interconnects on the EM is further investigated with various failure analysis techniques and three-dimensional finite element simulation. It is proposed that SM can influence EM when there is significant amount of vacancy accumulation due to SM in the cathode area which accelerates EM nucleation time. In the case of the MX structure, our experimental results show that SM and EM interaction occurs exactly below the via at the MX cathode side, leading to abrupt failures. On the other hand, in MX+1 structure, vacancies are likely to accumulate at the edge of upper metal lead during SM test, thus accelerating the failure during subsequent EM test. A failure mechanism model for stress evolution and void formation is proposed to provide insight into the interaction between these two failure mechanisms.

Effect of Electron Flow Direction and Via Number on Electromigration Mechanism for Copper Dual Damascene Interconnects

In this study, the effects of the via number and the current direction on electromigration characteristics in the dual-damascene Cu lines have been investigated. The results reveal an interesting difference in electromigration behavior of electron up- and down-flow directions on the multi-via structures. Increasing the via number results in a higher electromigration failure time and then reaches saturation for electron up-flow case. As for electron down-flow direction, the failure time is independent of the via number. Moreover, the failure time of Cu lines with via structure is lower than that without via structure. A higher current density at the triple junction site in the inner via is the possible mechanism, resulting in a shorter failure time and via-number independent. These observed effects are specific to Cu dual-damascene structures and can provide great technological implications in electromigration improvement.

Line-width dependency on electromigration performance for long and short copper interconnects

Experiments were performed to study the effect of metal line width on electromigration characteristics for Cu interconnects, and the results revealed completely different electromigration behavior for long and short metal lines. The extracted critical current density jc due to back stress effect can explain the electromigration width effect for long and short metal lines. For long metal lines, the electromigration times to failure were found to be increased with increasing the line width, and the critical current density jc is lower and slightly increased for the wider metal line. On the other hand, the electromigration failure time was observed to be inversely proportional to the line width in the case of short metal lines. Moreover, the back stress effect was decreased with increasing the line width, leading to the decreasing critical current density jc. These observed effects are specific to Cu technology and can have major technological implications for electromigration assessment.

Effect of Al-Trace Width on the Electromigration Failure Time of Flip-Chip Solder Joints

The effect of Al-trace width on electromigration (EM) in flip-chip solder joints was investigated experimentally. EM tests were performed on eutectic Sn-Ag solders with 40-μm- and 100-μm-wide Al traces. Under the same stressing conditions (0.5 A at 165°C), the failure time was 44.1 h for solder joints with 40-μm-wide traces and 250.1 h for solder joints with 100-μm-wide traces. The Al-trace width influenced both the current crowding and the Joule heating effects. Thus, both effects are responsible for the significant difference in failure time. Finite-element analysis was used to examine the current crowding effect in solder bumps with Al traces of the two different widths. The results showed that the current crowding effect was slightly higher in joints with 40-μm-wide traces. In addition, the temperature coefficient was used to measure the real temperatures in the solder bumps during EM. The results indicated that the width of the Al traces had a substantial influence on the Joule heating effect. The measured temperature in the solder bump was 218.2°C and 172.2°C for the bump with 40-μm- and 100-μm-wide Al traces, respectively. This difference in the Joule heating effect plays a crucial role in causing the difference in the failure time of solder joints with the two different widths.

Effect of copper barrier dielectric deposition process on characterization of copper interconnect

The effect of copper (Cu) barrier film deposition process on the Cu interconnects was investigated, including the waiting time between Cu chemical mechanical polishing and the barrier dielectric deposition, the preheating time, ammonia (NH3) plasma treatment prior to the barrier dielectric deposition, and various types of barrier dielectric. Effective treatment on the Cu surface ensures superior conductivity of the Cu interconnects and enhances the adhesion between Cu and the barrier film, causing a longer electromigration failure time. However, excessive thermal time (preheating, treatment, and deposition time) induces the Cu hillock defect. Furthermore, silicon nitride (SiN) film with a lower hydrogen content has better physical and reliability performances. Therefore, optimization of the Cu barrier deposition process is important to improve the performance of Cu interconnects.

Electromigration Failure Distributions of Cu/Low-$k$ Dual-Damascene Vias: Impact of the Critical Current Density and a New Reliability Extrapolation Methodology

We examine the effects of void morphology and critical current density (j <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) on the electromigration failure distributions of Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dual-damascene vias. Cu dual-damascene vias exhibit multiple modes of electromigration-induced voiding, and reliability is strongly dependent on the morphology of voids. We have developed a model of failure for dc and pulsed dc currents that allows prediction of failure time distributions for vias, taking into account void morphology. We obtain good agreement between the model predictions and experimental data for all observed void morphologies. The model demonstrates that while the concept of ldquoimmortalityrdquo is valid for individual conductors, it cannot be applied to eliminate failure of all nominally identical conductors in large sample sizes that are typical of integrated circuits. We experimentally confirm the existence of resistance increase failures for test populations of nominally identical conductors stressed below the sample average j <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> . Moreover, failure time distributions for vias exhibit distortion from lognormal and saturation in the vicinity of j <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> , but they are predictable for all values of j. New reliability extrapolation procedures are required for accurate projection of electromigration lifetimes close to j <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> . We suggest that the description of the effects of j <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> on failure distributions of vias discussed here is generally valid irrespective of the choice of conductor and barrier layer materials, and we demonstrate equivalent characteristic behavior of electromigration failure time distributions for both Al and Cu interconnects. Our results also indicate that, in general, accurate modeling of j <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> for conductor failure requires consideration of both nucleation and growth phenomena, with the relative contribution of each process to j <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> being dependent on the voiding failure mode.

Modeling the electromigration failure time distribution in short copper interconnects

The electromigration (EM) lifetime in short copper interconnects is modeled using a previously developed means of generating realistic interconnect microstructures combined with the one-dimensional stress evolution equation of Korhonen et al. [J. Appl. Phys. 73, 3790 (1993)]. This initial analysis describes the void nucleation and subsequent growth in lines blocked at one end and terminated with a pad at the other. For short copper interconnects, the failure time is largely spent on void growth, and, for sufficiently short lines (≲50 mm), the growth is largely steady state. This allows for the development of a simple expression for the variation of the failure time with microstructure. Assuming that the diffusion activation energies are normally distributed, the permanence property of summed lognormals leads to a roughly lognormal distribution for EM failure times. Importantly for EM design rules, linear extrapolation on lognormal plot is found to slightly underestimate interconnect reliability.

Numerical Analysis for Electromigration of Cu Atom

The electromigration of Cu interconnection was investigated to solve the Huntigton's equation by numerical analysis. The Cu atoms moved toward anode from cathode and accumulated at the anode end. This result was in good agreement with the result previously derived by our theoretical analysis. The accumulation rate of Cu atoms increased with increasing in current density, but it was not so influenced by temperature. The characteristic of the rate of electromigration showed a liner relationship with current density and exponential relationship with temperature. This result agreed with the equation experimentally derived by Black. This result proved that numerical analysis of atom transport equation enables to predict of electromigration failure time.

Threshold electromigration failure time and its statistics for Cu interconnects

Integrated circuit chip metallization reliability under use conditions is extrapolated from failure distributions of test structures tested under accelerated conditions. Lognormally plotted electromigration failure time distributions for via/line contact configurations with no redundant conductive path usually display two features that are different from failure time distributions for configurations that have well-defined redundant conductive paths. First, the failure times are more widely distributed (larger standard deviation or σ), and second, the left portion of the distribution (early failures) bends downward (if the sample size is large enough) as the failure times become shorter, in contrast to the straight line behavior that is usually observed for structures with good redundancy. The downward deviation from a straight line distribution erodes the goodness of fit relative to the commonly used two-parameter (t50,σ) lognormal distribution model, and the large σ produces a lifetime projection under use conditions that can be unacceptable for chip reliability. A three-parameter lognormal distribution model (t50,σ,X0) greatly improves the goodness of fit, especially for the downward bending early failure region, and produces projected failure times that are acceptable for chip reliability. The third parameter, X0, is interpreted as the threshold failure time for the distribution, or the time needed to form the absolute minimum size void that will cause failure. All recorded failure times for a given distribution will be greater than X0. Failure distributions for a via/line configuration with no redundancy are compared to those for via/line configurations with varying degrees and types of redundancy to demonstrate the behavior.

Effect of Al trace dimension on electromigration failure time of flip-chip solder joints

The effect of Al-trace dimension on electromigration of flip-chip solder joints was investigated. The Al trace dimension was found to have a significant influence on the electromigration failure time. When joints with Al traces 100 µm wide were stressed by 1.0 A at 100°C, failure times were 35 h, 1,700 h, and >3,000 h for joints with Al traces that were 2,550 µm, 1,700 µm, and 850 µm long, respectively. Solder joints with Al traces 40 µm wide and 2,550 µm long failed instantly at 0.6 A. The Joule heating effect was found to be responsible for the huge difference in failure time.

エレクトロマイグレーションによる銅配線の原子移動数値解析

The electromigration of Cu interconnection was investigated to solve the Huntigton's equation by numerical analysis. The Cu atoms moved toward anode from cathode and accumulated at the anode end. This result was in good agreement with the result previously derived by our theoretical analysis. The accumulation rate of Cu atoms increased with increasing in current density, but it was not so influenced by temperature. The characteristic of the rate of electromigration showed a liner relationship with current density and exponential relationship with temperature. This result agreed with the equation experimentally derived by Black. This result proved that numerical analysis of Huntignton's equation enables to predict of electromigration failure time.