Electromigration Failure Mechanism Research Articles

Effect of βSn grain orientations on the electromigration-induced evolution of voids in SAC305 BGA solder joints

The electromigration (EM) failure of solder joints is closely related to the development of voids during EM. In this paper, an integrated approach combining experimentation and finite element simulation was employed to reveal the evolution of voids in solder joints under current stress. The results indicate that the quantity and volume of voids near the cathode consistently increase, while those close to the anode decrease. These asymmetric evolutions of voids are mainly due to the Sn flux, which is controlled by both current density and βSn grain orientation. The magnitude of Sn flux increases with higher current densities and larger angles γ between the c-axis of βSn and the current direction. The direction of Sn flux is more significantly influenced by the current direction rather than the βSn orientation, due to the weak anisotropic self-diffusion of Sn. Voids near the anode tend to shrink while those close to the cathode expand, parallel to the substrate, due to higher Sn flux distributions at the waists of voids, where current crowding is seen. Void splitting related to rapid Cu diffusion has been observed, leading to an abnormal increase in the number of voids near the cathode. This study enhances the understanding of the electromigration failure mechanisms involving void evolution in solder joints.

Research on Crystal Structure Evolution and Failure Mechanism during TSV-Metal Line Electromigration Process

The combined use of Through Silicon Via (TSV) and metal lines, referred to as TSV-metal lines, is an essential structure in three-dimensional integrated circuits. In-depth research into the electromigration failure mechanism of TSV and the microstructure evolution can serve as theoretical guidance for optimizing three-dimensional stacking. This article conducted electromigration experiments on TSV-metal line structural samples at current densities of 1.0 × 105 A/cm2, 5 × 105 A/cm2, and 1 × 106 A/cm2. Additionally, Electron Back Scattered Diffraction (EBSD) technology was employed to systematically investigate the microstructural evolution of the TSV-metal line structure profiles before and after the application of electrical testing. The results indicate that the current induces a change in the crystal orientation at the TSV-metal interface (TSV/metal interface) and the bottom metal line. This phenomenon notably depends on the initial angle between the grain orientation and the current flow direction. When the angle between the current direction and the grain orientations [001] and [010] is relatively large, the crystals are more likely to deviate in the direction where the angle between the grain orientation and the current is smaller. This is because, at this point, the current direction is precisely perpendicular to the <100> crystal plane family, where the atomic density is lowest, and the energy required for electron transport is minimal. Therefore, the current readily rotates in the direction of this crystal orientation. Before the electromigration tests, areas with a high level of misorientation were primarily concentrated at the TSV/metal interface and the corners of the TSV-metal line. However, these areas were found to be more prone to developing voids after the tests. It is conjectured that the high misorientation level leads to elevated stress gradients, which are the primary cause of cracking failures in the TSV-metal line. As the current density increases from 5 × 105 A/cm2 to 1 × 106 A/cm2, the electromigration failure phenomena in the TSV become even more severe.

Understanding electromigration failure behaviors of narrow cobalt lines and the mechanism of reliability enhancement for extremely dilute alloying of manganese oxide

Self-forming barriers for copper (Cu) interconnect metallization are well developed. However, the self-forming-barrier process and associated electromigration behaviors of narrow lines of cobalt (Co), a new interconnect wiring material for sub-10-nm semiconductor device nodes, are yet to be explored. In this study, we present an all-wet electroless trench-filling process to fabricate narrow (100 nm) lines of Co and MnO-added Co [Co(MnO)], then thermally annealed to some extent (400 °C/30 min) prior to electromigration testing. Empirical data obtained from accelerated electromigration testing, including failure lifetimes, current-density scaling factors, activation energies and physical failure profiles, consistently show that electromigration reliability of the Co lines is markedly enhanced by 0.1% added MnO. Transmission electron microscopy and focused ion beam imaging, along with dynamic adhesion strength data, reveal that the enhancement is related to annealing-induced segregation and dispersion of MnO particles at the interface with SiO2, ensuring adhesion of Co on SiO2, preventing interfacial interdiffusion and stuffing electromigration pathways. The adhesion strength, microstructures and Joule-heating data of Co and Co(MnO) are provided for the discussion of the differences in their electromigration performance and failure mechanism. Comments on electroless-plated Co as a new interconnect material are also given.

Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study.

To meet the demands for miniaturization and multi-functional and high-performance electronics applications, the semiconductor industry has shifted its packaging approach to multi-chip vertical stacking. Among the advanced packaging technologies for high-density interconnects, the most persistent factor affecting their reliability is the electromigration (EM) problem on the micro-bump. The operating temperature and the operating current density are the main factors affecting the EM phenomenon. Therefore, when a micro-bump structure is in the electrothermal environment, the EM failure mechanism of the high-density integrated packaging structure must be studied. To investigate the relationship between loading conditions and EM failure time in micro-bump structures, this study established an equivalent model of the vertical stacking structure of fan-out wafer-level packages. Then, the electrothermal interaction theory was used to carry out numerical simulations in an electrothermal environment. Finally, the MTTF equation was invoked, with Sn63Pb37 as the bump material, and the relationship between the operating environment and EM lifetime was investigated. The results showed that the current aggregation was the location where the bump structure was most susceptible to EM failure. The accelerating effect of the temperature on the EM failure time was more obvious at a current density of 3.5 A/cm2, which was 27.51% shorter than 4.5 A/cm2 at the same temperature difference. When the current density exceeded 4.5 A/cm2, the change in the failure time was not obvious, and the maximum critical value of the micro-bump failure was 4 A/cm2~4.5 A/cm2.

The Study of the Reliability of Complex Components during the Electromigration Process

With the increasing number of inputs and outputs, and the decreasing interconnection spacing, electrical interconnection failures caused by electromigration (EM) have attracted more and more attention. The electromigration reliability and failure mechanism of complex components were studied in this paper. The failure mechanism and reliability of complex components during the electromigration process were studied through the simulation and the experiment, which can overcome the limitation of experimental measurement at a micro-scale. The simulation results indicated that the solder joint has obvious current crowding at the current inlet, which will significantly enhance the electromigration effect. Based on the atomic flux divergence method, the void formation of solder joints can be effectively predicted, and life prediction can be more accurate than Black's equation. Experimental results indicated that the resistance of the daisy chain could be significantly increased with the process of void formation in the solder and corrosion of the leads. Moreover, the growth of intermetallic compounds can be obviously promoted under current stress. The main composition of the intermetallic compounds changes from almost entirely Cu5Sn6 to Cu5Sn6 and Cu3Sn; the cracks can be detected at the Cu3Sn layer. Specifically, the mean time to failure is 1065 h under 1.4 A current and 125 °C based on IPC-9701A guidelines.

Electromigration failure in inkjet-printed Ag conductive lines

Electromigration (EM) is crucial to the reliability of most conductive lines used in electronics. In the present study, the EM characteristics of inkjet-printed Ag conductive lines were analyzed under various EM acceleration conditions to comprehend the EM failure behaviors associated with inkjet-printed Ag lines with nanoparticle inks. The evolution of the porosity level in the microstructure of the inkjet-printed Ag lines during the EM test was investigated to locate the EM failure positions in the line and identify the main driving force for EM mass transport. Two theoretical models (resistometric and Black’s) were employed to analyze the activation energy and expected lifetime of inkjet-printed Ag lines. This study indicates that the EM of Ag cations is directed toward the cathode by the direct force resulting from the electric field–ion interaction, resulting in EM failure near the anode and hillock formation near the cathode of the inkjet-printed Ag lines. The activation energy computed from the theoretical models suggests that the surface diffusion of Ag through the inkjet-printed line plays an important part in the EM failure mechanism. This research was a pioneering attempt to experimentally investigate the EM performance of inkjet-printed Ag lines.

Microstructure evolution and failure mechanism of electromigration in Ag-alloy bonding wire

Ag-alloy bonding wire has excellent physical properties and is widely applied in microelectronics, but growing concerns about circuit failure induced by electromigration (EM) have raised doubts about this material. One point of frequent debate is the diffusion mechanism. This study provides a novel perspective by investigating the evolution of the microstructure via electron backscatter diffraction (EBSD) to settle the controversy over the diffusion mechanism of Ag-alloy bonding wire during EM. Particular focuses are the propensity for grain growth, the effects of the coincidence site lattice (CSL) on the grain boundary network, the texture transition, and the influence of thermal energy during EM. A stage-like transition in the dominant diffusion mechanism in different stages of EM is proposed and substantiated from the viewpoint of microstructure evolution.

Enhancement of Electromigration Reliability of Electroless-Plated Nanoscaled Copper Interconnects by Complete Encapsulation of a 1 nm-Thin Self-Assembled Monolayer

The downsizing of integrated circuits for the upcoming technology nodes has brought attention to sub-2 nm thin organic/inorganic materials as an alternative to metallic barrier/capping layers for nanoscaled Cu interconnects. While self-assembled monolayers (SAMs) serving as the barrier materials for copper metalized films are well studied, electromigration (EM) of Cu interconnects encapsulated by SAMs is an untouched research topic. In this study, we report an all-wet encapsulating process involving SAM seeding/encapsulating and electroless narrow-gap filling to fabricate nanoscaled copper interconnects that are completely encapsulated by a 1 nm-thin amino-based SAM, subsequently annealed to some extents prior to EM testing. Both annealing and SAM encapsulation retard EM of the Cu interconnects tested at current densities on orders of 108–109 A cm−2. Particularly, SAM encapsulation quintuples the lifetime of, for example, as-fabricated Cu interconnects from 470 to 2,890 s. Electromigration failure mechanisms are elucidated from analyses of activation energies and current-density scale factors obtained from the accelerated EM testing. The importance of SAM qualities (e.g., ordering and layered structure) as a prerequisite for the reliability enhancement cannot be overestimated, and the results of the SAM quality evaluation are presented. The mechanism of reliability enhancement is also thoroughly discussed.

Layer Thickness Effect on Lifetime of Copper Oxide Passivated Plasma Etched Copper Line

Previously, authors reported that copper oxide could be a good passivation material for the copper line because it prevented copper diffusion to adjacent layer at the high temperature. In this paper, the copper oxide thickness effect on the electromigration failure mechanism is studied. The copper oxide passivation layer was formed by exposing the copper line to the oxygen plasma in a parallel-plate plasma etcher. The copper oxide passivation layer has a smooth surface and a crystalline structure. The copper line with a very thin copper oxide passivation layer has an electromigration lifetime similar to that of the unpassivated copper line. However, the lifetime deteriorates with the increase of the copper oxide thickness due to the enlargement of the mechanical and thermal stress mismatches between the bulk copper film and the passivation layer. Therefore, the thickness of the copper oxide is critical to the effectiveness of its passivation function.

Electromigration failure mechanisms of 〈1 1 1〉 -oriented nanotwinned Cu redistribution lines with polyimide capping

Electromigration (EM) mechanisms are well studied in damascene copper lines capped with inorganic dielectrics. However, EM in Cu redistribution lines (RDLs) capped by organic layers is not well-understood. In this study, nanotwinned copper (nt-Cu) is adopted, which has high mechanical strength as well as excellent electrical resistivity. We designed EM test vehicles with four-point probes to measure the lifetime of RDLs and examine the failure mechanisms of the Cu RDLs. The length of the RDLs was 800 µm, the width was 10 µm, and the height was 5 µm. The samples were tested at 200 °C, with current densities of 1.0 × 106 A/cm2. The results indicated that there were two main failure mechanisms, including EM-induced voiding and oxidation of Cu RDLs. The measured EM lifetime of nt-Cu RDLs is 4 times longer than that of regular Cu RDLs.

Solder Volume Effect on Electromigration Failure Mechanism of Cu/Ni/Sn-Ag Microbumps

Effects of solder volume on the electromigration (EM) failure mechanism of Cu/Ni/Sn-2.5Ag microbumps were systematically investigated at 150 °C with a current density of $1.5\times 10 ^{5}$ A/cm2. While the electrical resistances of Cu/Ni/Sn-Ag microbump with large solder volume increased quickly, those with small solder volume increased slowly, which depends on the difference in solder volume effect on the intermetallic compound formation mechanisms. For a structure with large solder volume, the Ni barrier layer was extensively consumed due to substantial reaction between Ni barrier and large solder volume. For a structure with small solder volume, the initial Ni barrier structure was preserved due to the limited volume of solder reacting with Ni barrier, which mainly contributes to better EM reliability of Cu/Ni/Sn-Ag microbump.

Electromigration Study of Plasma Etched Copper Lines with Copper Oxide Capping Layers

Copper (Cu) is a widely used interconnection material in integrated circuits (ICs) and large area thin film transistor (TFT) arrays. Chemical mechanical polishing (CMP) is the most popular production method in etching Cu fine lines [1,2]. Cu cannot be etched with a conventional plasma etching process at the room temperature because of the low volatility of copper halides [3,4]. Kuo’s group invented a plasma-based Cu etch method that includes two steps: the conversion of Cu into CuClx or CuBrx with a Cl- or Br-containing plasma and the subsequent removal of the halide by dipping in a dilute HCl solution [5-7]. The complete process, which can be carried out at room temperature, has been used to fabricate BiCMOS ICs and TFT LCDs [8,9]. The reliability of the Cu line can be evaluated using the electromigration (EM) method [10]. EM tests on Cu lines with different capping layers (e.g., TiW, Mo), which could prevent Cu oxidation, have been reported [11-13]. In this study, the influence of the copper oxide (CuOx) capping layer on the EM reliability is studied.The Mo/Cu stack was sputter deposited on a Corning glass substrate and etched into a 4-point pattern by the plasma-based etching method in a parallel-plate RIE reactor (PlasmaTherm 700C) at room temperature. The Cu chlorination reaction was conducted in CF4/HCl 5/20 sccm at 70 mTorr and 600 W for 2 minutes. Then, the CuClx layer was dissolved in a H2O:HCl (8:1 v/v) solution for 1 min. The Mo barrier layer was etched in CF4/O2 10/10 sccm at 60 mTorr and 600 W for 2 minutes. In order to form the CuOx capping layer, the Cu line was exposed to the O2 plasma at 200 mTorr and 100W for 3 minutes in the same PlasmaTherma reactor but under the plasma etching mode. For the comparison purpose, a control sample, i.e., the Mo/Cu line without the CuOx capping layer, was prepared and EM stressed. All EM tests were done at room temperature under the fixed current densities (J) condition.Figure 1 shows the resistance-time (R-t) and temperature-time (T-t) curves of Mo/Cu/CuOx lines stressed at different current densities. The resistance increases slightly with the stress time and jumps sharply at the line broken point. Also, the line broken time shortens with the increase of the current density. The line broken process starts from voids formation at grain boundaries followed by voids merging [11-13]. The T-t curves were calculated by the JEDEC standard guidelines of JESD33-B [14] modified with an iteration method. The change of the T-t curve follows that of the R-t curve since the temperature increase is caused by Joule heating. The extent of heat dissipation is dependent on the heat dissipation rate of the CuOx capping layer of which the composition changes during the EM stress.Figure 2 shows top views of a Mo/Cu/CuOx line at different stress times under J = 0.41×106 A/cm2. The original line has the aquamarine color. The color becomes lighter when stressed. Eventually, the broken region became dark. The line color change is a good indication of the change of the composition of the passivation layer, which is temperature dependent.The detailed EM failure mechanism with the CuOx composition change will be presented. Advantages of the CuOx passivation layer will also be discussed. Authors acknowledge the financial support of this work through NSF CMMI project 1633580. 1. A. Gladkikh and Y. Lereah, APL, 66(10), 1214-1215 (1995).2. C. S. Hau-Riege, et al., JAP, 96(10), 5792-5796 (2004).3. Y. Kuo and J.R. Crowe, JVST A, 8(3), 1529-1532 (1990).4. H. Miyazaki, et al., JVST B, 15(2), 237-240 (1997).5. Y. Kuo and S. Lee, JJAP, 39(3A), L188 (2000).6. S. Lee and Y. Kuo, JES, 148(9), G524-G529 (2001).7. Y. Kuo and S. Lee, APL, 78(7), 1002-1004 (2001).8. Y. Kuo and S. Lee, Vacuum, 74(3-4), 473-477 (2004).9. J. Yang, et al., ECS Trans., 16(9), 13 (2008).10. C. S. Hau-Riege, Microelectronics Reliability, 44(2), 195-205 (2004).11. M. Li, J. Q. Su and Y. Kuo, ECS Trans., 89(3), 87-92 (2019).12. J. Q. Su, M. Li and Y. Kuo, ECS Trans., 90(1), 65-72 (2019).13. J. Q. Su, M. Li, Y. Kuo and S. Hamaguchi, ECS Trans., 92(5), 39-46 (2019).14. EIA/JESD33-B, Standard Method of Measuring and Using the Temperature Coefficient of Resistance to Determine the Temperature of a Metallization Line (2004). Figure 1

Ni Barrier Symmetry Effect on Electromigration Failure Mechanism of Cu/Sn–Ag Microbump

Ni barrier symmetry effect on the electromigration (EM) failure mechanism of Cu/Sn–Ag microbump were systematically investigated by studying the intermetallic compound (IMC) growth characteristics at 150 °C with a current density of 1.5 × 105 A/cm2. In the symmetric Ni barrier structure, Cu diffusion to Sn–Ag solder was restricted by the Ni barrier at both interfaces and the Ni3Sn4 phase formed by the inter-diffusion between Ni and Sn atoms just after bonding, which was gradually transformed to (Ni,Cu)3Sn4 phase and later to (Cu,Ni)6Sn5 during current stressing with relatively slow resistance increase with time. By the way, in the asymmetric structure, extensive Cu6Sn5 phase grew by the inter-diffusion between Cu and Sn atoms due to there is no Ni barrier at the upper interface, which was rapidly transformed into only Cu6Sn5 and Cu3Sn IMCs during electron downward flow, with relatively fast resistance increase with time. Therefore, the symmetric Ni barrier structure is very effective in restricting extensive IMC reactions during EM of Cu-solder microbump structure.

A new failure mechanism of electromigration by surface diffusion of Sn on Ni and Cu metallization in microbumps

Microbumps in three-dimensional integrated circuit now becomes essential technology to reach higher packaging density. However, the small volume of microbumps dramatically changes the characteristics from the flip-chip (FC) solder joints. For a 20 µm diameter microbump, the cross-section area and the volume are only 1/25 and 1/125 of a 100 µm diameter FC joint. The small area significantly enlarges the current density although the current crowding effect was reduced at the same time. The small volume of solder can be fully transformed into the intermetallic compounds (IMCs) very easily, and the IMCs are usually stronger under electromigration (EM). These result in the thoroughly change of the EM failure mechanism in microbumps. In this study, microbumps with two different diameter and flip-chip joints were EM tested. A new failure mechanism was found obviously in microbumps, which is the surface diffusion of Sn. Under EM testing, Sn atoms tend to migrate along the surface to the circumference of Ni and Cu metallization to form Ni3Sn4 and Cu3Sn IMCs respectively. When the Sn diffuses away, necking or serious void formation occurs in the solder, which weakens the electrical and mechanical properties of the microbumps. Theoretic calculation indicates that this failure mode will become even significantly for the microbumps with smaller dimensions than the 18 µm microbumps.

Effect of Current Densities on the Electromigration Failure Mechanisms of Flip-Chip Sn-Ag Solder Bump

Effect of Current Densities on the Electromigration Failure Mechanisms of Flip-Chip Sn-Ag Solder Bump

Study of electromigration-induced formation of discrete voids in flip-chip solder joints by in-situ 3D laminography observation and finite-element modeling

In the microelectronics industry the flip-chip (FC) technology is broadly used to enhance the packaging density. However, the small size and the unique geometry of the FC solder joints induce the electromigration (EM) reliability issue. In this study, a pair of lead-free solder joints (SAC1205) was EM tested by a current of 7.5 × 103 A/cm2. During the tests, X-ray laminography was applied to observe the microstructure evolution in-situ. Laminography enables the non-destructive observation of the bump microstructure and allows for a quantitative three-dimensional (3D) analysis. After EM testing for 650 h, a new EM failure mechanism was found, differing from the two well-known models, the pancake void propagation and the under-bump-metallization dissolution. Here, a few pre-existing small voids grew and simultaneously many new voids formed and grew over the entire EM testing period. Most of the nucleating voids were distributed in the current crowding region, a few also located in the low-current-density region. As the testing time increased, voids increasingly coalesced with each other, forming a porous network which occupied a large part of the interface area and caused the EM failure. A finite-element (FE) method was then applied to analyze the interplay between the microstructure evolution and current density redistribution. A series of 3D FE models was built based on the laminography images for the different testing stages. The current density distribution from the FE analysis indicates that the formation of discrete voids did not affect the global current density distribution until a major coalescence of the voids occurred. The relieving of the global current crowding in the pancake void model was not found in this new EM failure mechanism. It was the local current crowding around individual void found in the new mechanism that is held responsible for the EM retardation.

1/f noise measurements for faster evaluation of electromigration in advanced microelectronics interconnections

The use of 1/f noise measurements is explored for the purpose of finding faster techniques for electromigration (EM) characterization in advanced microelectronic interconnects, which also enable a better understanding of its underlying physical mechanisms. Three different applications of 1/f noise for EM characterization are explored. First, whether 1/f noise measurements during EM stress can serve as an early indicator of EM damage. Second, whether the current dependence of the noise power spectral density (PSD) can be used for a qualitative comparison of the defect concentration of different interconnects and consequently also their EM lifetime t50. Third, whether the activation energies obtained from the temperature dependence of the 1/f noise PSD correspond to the activation energies found by means of classic EM tests. In this paper, the 1/f noise technique has been used to assess and compare the EM properties of various advanced integration schemes and different materials, as they are being explored by the industry to enable advanced interconnect scaling. More concrete, different types of copper interconnects and one type of tungsten interconnect are compared. The 1/f noise measurements confirm the excellent electromigration properties of tungsten and demonstrate a dependence of the EM failure mechanism on copper grain size and distribution, where grain boundary diffusion is found to be a dominant failure mechanism.

The Materials and Reliability of Power Electronics Devices

Small signal commercial electronics have traditionally been designed to operate at temperatures from 0°C to 70°C. Increased temperature often compromises performance and when combined with the higher voltages, current densities, and heat dissipations associated with power electronics can result in an increased susceptibility to oxide breakdown, electromigration, and other catastrophic on-chip failure mechanisms. Furthermore, the large temperature swings of extreme environments and the rapid temperature cycles resulting from turning on and off large amounts of power can cause fatigue of the die, wires, die attach, and substrate in the package. The course sequence focuses on understanding the device technologies, and developing packaging and thermal management strategies that mitigate risks related to the operating temperatures and large temperature cycles common in extreme temperature and power electronics. Included will be issues related to the effect of high and low operating temperatures on device and packaging reliability, power device (IGBT, MOSFET, BJT) and material (Si, SiC, GaN) selection, passive component and packaging materials selection, thermal management, and assembly of reliable high power and extreme temperature electronic systems. Finally, failure mechanism models for high temperature and power electronics will be presented together with a discussion of design options to mitigate failure. Topics covered : Reliable design and manufacture of power semiconductor components;Reliable design of power inverters and converters;Effects of temperature on device performance and reliability;Reliable packaging of power modules and assemblies. The development of robust and reliable power electronic systems for sustainable energy systems requires an understanding of the fundamental degradation processes that can cause failure at the device, interconnection, and packaging level in the environments encountered in a wide range of energy systems applications. The course sequence will present the dominant failure mechanisms at each of these levels, along with selected models and reliability assessment methodologies. Mechanisms to be covered include degradation in GaN and SiC devices; fatigue and fracture of wirebonds, die attach, and substrates in power electronic modules; corrosion and conductive filament formation in boards; and fatigue of solder joints. Wide bandgap semiconductors are extremely attractive for the gamut of power electronics applications. Of the various materials and device technologies, the AlGaN/GaN high-electron mobility transistor has been developed and has reached the market. While GaN device and circuit technology is poised to break out in the commercial arena, certain risks or barriers to entry in the market should not be overlooked. The relative technology immaturity of GaN with respect to Silicon and GaAs leave issues like long-term reliability unanswered. The courses also present the main degradation mechanisms of GaN-based HEMTs devices.

Mode II electromigration failure mechanism in Sn-based Pb-free solder joints with Ni under-bump metallization

Early electromigration (EM) failure mechanism, also known as Mode II EM failure in Sn-based Pb-free solder joints with Ni under-bump metallization (UBM) is studied. A numerical model was built to incorporate interdiffusion and EM, and to investigate the effect of Sn crystal orientation. Results show that when the c axis of Sn has a close alignment to the current direction, intermetallic compound (IMC) growth is enhanced by both EM and extremely fast interstitial diffusion of Ni in the solder. The combined process results in IMC dissolution from the cathode side of the solder joint and causes EM failure by UBM depletion. Theoretical predictions are consistent with experimental observations.

Assessment of Influence of Impedance Mismatch in ULSI Devices on Electromigration of Copper Interconnection Lines

In this work, the impact of impedance mismatch between on-die CMOS drivers and driven transmission lines on electromigration (EM) and Joule-heating failure mechanisms has been qualitatively studied. Signals corrupted by the impedance mismatch were experimentally measured within a 45-nm CMOS technology ULSI test chip. The signals' current waveforms were obtained using a SPICE simulator. These voltage and current waveforms have been taken as a basis for our calculations. The results reveal that distortions of current shape, which are caused by the mismatched output impedance of a CMOS driver, lead to substantial aggravation of the EM and Joule heating in a driven line. Furthermore, it was found that the impedance mismatch causes serious modifications of current shape of a CMOS inverter connected to the far end of the line. This in turn aggravates both EM and Joule heating in the next-stage line that loads this CMOS inverter.