Electromigration Study of Plasma Etched Copper Lines with Copper Oxide Capping Layers

Abstract

Copper (Cu) is a widely used interconnection material in integrated circuits (ICs) and large area thin film transistor (TFT) arrays. Chemical mechanical polishing (CMP) is the most popular production method in etching Cu fine lines [1,2]. Cu cannot be etched with a conventional plasma etching process at the room temperature because of the low volatility of copper halides [3,4]. Kuo’s group invented a plasma-based Cu etch method that includes two steps: the conversion of Cu into CuClx or CuBrx with a Cl- or Br-containing plasma and the subsequent removal of the halide by dipping in a dilute HCl solution [5-7]. The complete process, which can be carried out at room temperature, has been used to fabricate BiCMOS ICs and TFT LCDs [8,9]. The reliability of the Cu line can be evaluated using the electromigration (EM) method [10]. EM tests on Cu lines with different capping layers (e.g., TiW, Mo), which could prevent Cu oxidation, have been reported [11-13]. In this study, the influence of the copper oxide (CuOx) capping layer on the EM reliability is studied.The Mo/Cu stack was sputter deposited on a Corning glass substrate and etched into a 4-point pattern by the plasma-based etching method in a parallel-plate RIE reactor (PlasmaTherm 700C) at room temperature. The Cu chlorination reaction was conducted in CF4/HCl 5/20 sccm at 70 mTorr and 600 W for 2 minutes. Then, the CuClx layer was dissolved in a H2O:HCl (8:1 v/v) solution for 1 min. The Mo barrier layer was etched in CF4/O2 10/10 sccm at 60 mTorr and 600 W for 2 minutes. In order to form the CuOx capping layer, the Cu line was exposed to the O2 plasma at 200 mTorr and 100W for 3 minutes in the same PlasmaTherma reactor but under the plasma etching mode. For the comparison purpose, a control sample, i.e., the Mo/Cu line without the CuOx capping layer, was prepared and EM stressed. All EM tests were done at room temperature under the fixed current densities (J) condition.Figure 1 shows the resistance-time (R-t) and temperature-time (T-t) curves of Mo/Cu/CuOx lines stressed at different current densities. The resistance increases slightly with the stress time and jumps sharply at the line broken point. Also, the line broken time shortens with the increase of the current density. The line broken process starts from voids formation at grain boundaries followed by voids merging [11-13]. The T-t curves were calculated by the JEDEC standard guidelines of JESD33-B [14] modified with an iteration method. The change of the T-t curve follows that of the R-t curve since the temperature increase is caused by Joule heating. The extent of heat dissipation is dependent on the heat dissipation rate of the CuOx capping layer of which the composition changes during the EM stress.Figure 2 shows top views of a Mo/Cu/CuOx line at different stress times under J = 0.41×106 A/cm2. The original line has the aquamarine color. The color becomes lighter when stressed. Eventually, the broken region became dark. The line color change is a good indication of the change of the composition of the passivation layer, which is temperature dependent.The detailed EM failure mechanism with the CuOx composition change will be presented. Advantages of the CuOx passivation layer will also be discussed. Authors acknowledge the financial support of this work through NSF CMMI project 1633580. 1. A. Gladkikh and Y. Lereah, APL, 66(10), 1214-1215 (1995).2. C. S. Hau-Riege, et al., JAP, 96(10), 5792-5796 (2004).3. Y. Kuo and J.R. Crowe, JVST A, 8(3), 1529-1532 (1990).4. H. Miyazaki, et al., JVST B, 15(2), 237-240 (1997).5. Y. Kuo and S. Lee, JJAP, 39(3A), L188 (2000).6. S. Lee and Y. Kuo, JES, 148(9), G524-G529 (2001).7. Y. Kuo and S. Lee, APL, 78(7), 1002-1004 (2001).8. Y. Kuo and S. Lee, Vacuum, 74(3-4), 473-477 (2004).9. J. Yang, et al., ECS Trans., 16(9), 13 (2008).10. C. S. Hau-Riege, Microelectronics Reliability, 44(2), 195-205 (2004).11. M. Li, J. Q. Su and Y. Kuo, ECS Trans., 89(3), 87-92 (2019).12. J. Q. Su, M. Li and Y. Kuo, ECS Trans., 90(1), 65-72 (2019).13. J. Q. Su, M. Li, Y. Kuo and S. Hamaguchi, ECS Trans., 92(5), 39-46 (2019).14. EIA/JESD33-B, Standard Method of Measuring and Using the Temperature Coefficient of Resistance to Determine the Temperature of a Metallization Line (2004). Figure 1