Electromigration Degradation Research Articles

Effect of Sn grain orientation on electromigration degradation mechanism in high Sn-based Pb-free solders

Electromigration induced damage strongly depends on Sn-grain orientation in Pb-free solders. Rapid depletion of intermetallic compounds and under bump metallurgy led to significant damages caused by the fast diffusion of Cu and Ni along the c axis of Sn crystals. When the c axis of Sn grain is not aligned with the current direction, electromigration (EM) damage is dominated by Sn self-diffusion, which takes longer to occur. This is a direct proof of the highly anisotropic diffusion behavior in Sn. Due to the presence of twin structures and stable Ag3Sn network, SnAg(Cu) solders are less susceptible to grain orientation effects and showed better EM performance than SnCu solders.

Localization and Analysis of Metal-Coating-Related Electromigration Degradation in the 65 nm Technology Node

Abstract With the introduction of 65 nm technology, the cross-sectional dimensions of copper interconnect in some layers are now smaller than 100 nm, which translates to current densities on the order of several MA/cm2. Electromigration as a root cause for chip failure is thus a major concern and is still being examined. In this article, the authors present recent failure analysis studies on metal-coated copper interconnects, using OBIRCH techniques in combination with FIB cross-sectioning and SEM and TEM imaging.

A model for electromigration-induced degradation mechanisms in dual-inlaid copper interconnects: Effect of microstructure

A developed physical model and a simulation algorithm are used to predict electromigration (EM)-induced stress evolution in dual-inlaid copper interconnects. Incorporation of all important atom migration driving forces into the mass balance equation and its solution, together with the solution of the coupled electromagnetics and elasticity problems, allows the simulation of EM-induced degradation in a variety of dual-inlaid copper interconnect segments with different dominant paths for mass transport [V. Sukharev and E. Zschech, J. Appl. Phys. 96, 6337 (2004)]. The results of the numerical simulation have been proven experimentally by EM degradation studies on fully embedded dual-inlaid copper interconnect test structures and by subsequent microstructure analysis, mainly based on electron backscatter diffraction (EBSD) data. The EM-induced void formation and its virtual movement and growth in a copper interconnect were continuously monitored in an in situ scanning electron microscopy experiment. The copper microstructure, particularly the orientation of grains and grain boundaries, was determined with EBSD. It has a significant influence on grain boundary diffusivity and consequently on the mass transport along grain boundaries. For interconnects with interfaces that resist atomic transport and where grain boundaries are the important pathways for atom migration [E. Zschech et al., Z. Metallkd. 96, 996 (2005)], degradation and failure processes are completely different for microstructures with randomly oriented grain boundaries compared with “bamboolike” microstructures. The correspondence between simulation results and experimental data indicates the applicability of the developed model for optimization of the physical and electrical design rules. Simulation-based optimization of the interconnect architecture, segment geometry, material properties, and some of the process parameters can produce on-chip interconnect systems with a high immunity to EM-induced failures.

Modeling of the Degradation Electromigrational Processes in Structures with Intercrystallite Potential Barriers

The electromigration degradation model of nonlinear electrical properties of non‐uniform structures with intercrystallite potential barriers is developed. It allows connecting the increasing of near surfaces concentration of volume donors by their migration in electrical field at heating up structures by means of electrical current in the process of degradation. It results in experimentally observed deterioration varistoral properties, deterioration and asymmetrical deformation of currentvoltage characteristics during their exploitation.

Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects

The degradation of IC interconnects due to electromigration (EM) is strongly influenced by physical defects and imperfections on interconnect traces that significantly accelerate EM damage through increased current density and elevated temperature. In this work, an IC reliability simulator is developed to incorporate the effect of these physical defects on circuit interconnect reliability. Based on a statistical defect modeling approach, circuit-level reliability with defective interconnects under EM degradation is evaluated. This has also been successfully integrated into a tool called ARET. Additionally, an approach for identifying circuit reliability hotspots has also been developed. Based on this hotspot identification, the concept of local design-for-reliability (LDFR) is proposed for improved circuit-level reliability under electromigration.

Electromigration degradation mechanism for Pb-free flip-chip micro solder bumps

The electromigration (EM) of flip chip interconnect composed of Pb-free SnAgCu micro solder bump and Ni under bump metallization (UBM) is studied by accelerated current stress test. The process of void growth at the cathode side of the bump and resistance degradation process are investigated by physical analysis using SEM and Infrared microscope. EM degradation process for SnAgCu solder bump shows drastic change over time in degree of resistance shift owing to variation of contact diameter and UBM layer structure. UBM metal diffusion and local Joule heating caused by current crowding play important roles in voiding degradation process.

Wear out failure mechanisms in aluminium and gold based LDMOS RF power applications

In this paper we will compare the electromigration and hot carrier properties of the old (gold based) and new (aluminium based) metallisation schemes as used in RF base station power amplifiers manufactured by Philips Semiconductors. We will show that the latest generation shows excellent reliability performance while the RF performance has been strongly enhanced. This has been obtained by optimizing the process and device architecture. Both results of electromigration measurements on test structures and electromigration degradation of full devices will be shown. It is concluded that the latest generation LDMOS RF amplifiers shows excellent RF and reliability performance while using an aluminium based metallisation scheme.

Monte Carlo simulation of electromigration phenomena in metallic lines

The electromigration (EM) of metallic lines is studied in terms of competition between biased processes taking place in a random resistor network. The effects associated with the transport of mass and with the consequent growth of the internal stress are accounted for by stochastic generation and recovery of voids, driven by the external current. Monte Carlo simulations enable us to successfully investigate within a unified theoretical framework a variety of relevant aspects of EM degradation. Here, we present an implementation of the model to rectangular networks. In this manner it is possible to study geometrical effects. An excellent agreement is found between the simulation results and the experimental findings concerning the dependence of the failure process upon the length of the metallic line.

Electromigration threshold in copper interconnects

The electromigration threshold in copper interconnects is reported in this study. The length-dependent electromigration degradation rate is observed and quantified in the temperature range of 295–400 °C. Based on the Blech electromigration model [I. A. Blech, J. Appl. Phys. 47, 1203 (1976)], a simplified equation is proposed to analyze the experimental data from various combinations of current density and interconnect length, as well as to estimate the electromigration threshold product of current density and line length, (jL)th, at a certain temperature. The resulting (jL)th value appears to be temperature dependent, decreasing with increasing temperature in the tested range between 295 and 400 °C.

Logic synthesis for reliability: an early start to controlling electromigration and hot-carrier effects

Designing reliable CMOS chips involves careful circuit design, with attention directed to some of the potential reliability problems such as electromigration and hot-carrier effects. This paper considers logic synthesis to optimize, early in the design phase, against electromigration and hot-carrier degradation. The electromigration and hot-carrier effects are estimated at the gate level using signal activity measure (average number of transitions at circuit nodes). Results on MCNC synthesis benchmarks show that logic can be synthesized to optimize for higher reliability and lower silicon area. A minimum-area circuit is usually not associated with highest reliability. >

Fast Thermal Cycling - Enhanced Electromigratton Failures in Si/TiSi2W-Ti/Al-Si-Cu Multilayer Contacts

AbstractFailure mechanisms of TiSi2/W-Ti(15%)/Al-Si(l%)-Cu(2%) multilayer thin film contact to silicon shallow junction (0,25 μm) have been investigated. Both a fast temperature cycling (with 300 ms thermal cycle period) and a high constant temperature were used as means for the degradation processes acceleration. We have shown that stress time could be reduced by the factor of 10 or more if the temperature of adjacent contact region was cycled by a pulsed electrical current passed through the semiconductor region lying under the investigated contacts. Our data have also indicated that W-Ti barrier layer serves to reduce drastically the electromigration degradation of thin film contacts for failures caused by an increase in junction leakage on the one hand and on the other hand it serves to intensify the electromigration degradation caused by an increase in contact resistance. These distinctions have been explained through structural-morphological investigations of the contact layers surface morphology. They showed a reduction in size of crystallines of the sputter deposited Al-Si-Cu top layer with W-Ti barrier layer present.

The Berkeley reliability simulator BERT: an IC reliability simulator

BERT (Berkeley reliability simulator) is a CAD tool developed for the purpose of design for reliability. This paper describes its intended application, the physical models and approaches used to simulate the hot electron effect, oxide time-dependent breakdown, electromigration, and bipolar transistor gain degradation.

IC reliability simulation

The motivation and challenges of IC reliability simulation are discussed. The reliability simulator BERT is used to illustrate the physical models and approaches used to simulate the hot-electron effect, oxide time-dependent breakdown, electromigration, and bipolar transistor gain degradation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Sequential observation of electromigration degradation in passivated Al stripes by interferometric optical scanning

It is shown that geometrical damages resulting from electrotransport in passivated Al stripes can easily be observed, with a resolution of a few nanometers, by means of an interferometric optical set allowing for sequential recordings in processing.