Electroless Au Plating Research Articles

Electroless Au Plating of CMOS Microelectrodes: Fabrication, Characterization, and Electrochemical Measurement

Electroless Au Plating of CMOS Microelectrodes: Fabrication, Characterization, and Electrochemical Measurement

Vertical Interconnections by Electroless Au Deposition on Electroless Ni Immersion Au Surface Finish

Electroless Au is used to vertically connect copper pillars with electroless Ni immersion Au surface finish on two stacked chips by a microfluidic electroless interconnection process. A very low bonding temperature of 50°C and a pressure-less bonding process can be achieved. The vertical interconnections are formed by a forced flow of electroless Au plating solution through a microchannel so that the reduced Au atoms self-assemble between the gaps of facing copper pillars to complete the interconnections. The deposited Au grains span the entire gap across the two copper pillars, suggesting that the rate-limiting step is more likely to be the nucleation rather than the growth of the Au grains. Four-point probe measurements show that the average resistance of the electroless-Au-bonded interconnections is low. Mechanical shear testing reveals that the bonding of the interconnections is strong. Furthermore, it is demonstrated that this process is capable of accommodating a high degree of pillar misalignment.

Electrical Resistance of Cu-Cu Interconnection Using Electroless Ni(P) and Au Plating

Electrical Resistance of Cu-Cu Interconnection Using Electroless Ni(P) and Au Plating

Interdiffusion during heteroepitaxial Au growth on Pd thin films by electroless Au plating (ELGP) at room temperature

Electroless Au plating (ELGP) on Pd thin films is performed. The ELGP time dependence on the surface morphology is investigated by a scanning electron microscope. Continuous nucleation and growth of hemispherical Au islands are observed as the plating time increases. Heteroepitaxial growth of the electroless plated Au on the Pd surface is confirmed by cross-sectional scanning transmission electron microscope images. Cross-sectional energy-dispersive X-ray spectroscopy reveals interdiffusion between the Pd atoms and the plated Au atoms at room temperature, which allows the formation of Au–Pd alloys. The heteroepitaxial Au growth on Pd is significant for reducing contact resistance of Au/Pd structures.

Single-molecule single-electron transistor (SM-SET) based on π-conjugated quinoidal-fused oligosilole and heteroepitaxial spherical Au/Pt nanogap electrodes

A single-molecule single-electron transistor (SM-SET) consisting of a π-conjugated quinoidal-fused oligosilole derivative, Si-2, of radius 0.75 nm and heteroepitaxial spherical (HS) Au/Pt nanogap electrodes is demonstrated. Si-2 with two inner silicon atoms and two ethylenethiol groups at both ends is chemisorbed by an S–Au bond between HS-Au/Pt nanogap electrodes fabricated by combining electron-beam lithography and electroless Au plating. An ideal Coulomb staircase, Coulomb oscillation, and Coulomb diamond were observed using the 1.5 nm Si-2 SM-SET, which were supported by theoretical results based on the orthodox model.

Heteroepitaxial spherical electroless Au-plated Pt-based nanogap electrodes of radius 5 nm and gap separation 0.7 nm

Heteroepitaxial growth is demonstrated by electroless Au plating (ELGP) on polycrystalline Pt surface and initial ultrafine-linewidth Pt nanogap electrodes, confirmed by scanning transmission electron microscope cross-sectional images, atomic-resolution scanning electron microscope images, and energy-dispersive X-ray spectroscopy elemental maps. The gap between a pair of spherical multidomain heteroepitaxial Au on Pt electrodes of radius 5 nm is controlled to a value as small as 0.7 nm by the self-termination mechanism of ELGP without short circuit. The heteroepitaxial spherical Au/Pt nanogap electrodes are found to be robust against annealing at temperatures up to 573 K.

Block-Copolymer-Based Au/Ag Nanoring Arrays with Widely Tunable Surface Plasmon Resonance

We demonstrate a simple route for fabricating Au/Ag nanoring arrays with widely tunable surface plasmon resonce using PS-b-P2VP copolymer templates. Ring-shaped Au dotted arrays are prepared by incorporating Au precursors into the PS-b-P2VP templates. Subsequently, electroless Au plating process enables us to make continuous Au nanoring structures, in which localized surface plasmon spectra cover the range from visible to near-IR regions. Finally, when the Au nanoring arrays are combined with silver-mirror reaction, Au/Ag bimetallic nanoring structures which can also tune the surface plasmon band are successfully fabricated on a wafer scale.

Fabrication of a membrane probe card using transparent film for three-dimensional integrated circuit testing

We fabricated a novel membrane probe card using a transparent film for the chip-level testing of a three-dimensional integrated circuit (3D-IC). In this membrane probe card, 20-µm-pitch Ni–Au contact bumps and Ti–Au wirings were formed on a biaxially oriented poly(ethylene naphthalate) (PEN) film. This probe card was fabricated using a low-temperature (lower than 100 °C) process, which included through-hole formation by a laser beam, photolithography, Ar plasma irradiation to improve the adhesion between the PEN film and the metal wiring, Ti–Au sputtering, Au electroplating, Ni electroplating, and electroless Au plating. The probe card has three characteristics: (1) fine pitch probes. (2) small-gap alignment between the probe card and the tested chip owing to transparency of the probe card, which offers high accurate probing. (3) damageless (low-load) probing owing to the compliancy of the PEN film. Using this probe card, we performed pre-bond testing of a 10-mm-square chip with Cu–SnAg bumps. The probing to 20-µm-pitch, 1,000 Cu–SnAg bumps and the pre-bond testing of thin Si chips were realized without causing damage to the chip even when chip was very thin (50 µm thick).

Impedance Spectroscopy of Highly Ordered Nano-Porous Electrodes Based on Au–AAO (Anodic Aluminum Oxide) Structure

Electrochemical measurements using the microelectrodes are increasingly utilized for the label-free detection of the small amount of biological materials such as DNA, protein, and cells. However, the interfacial electrode impedance increases and may hinder the detection of weak signals as the size of electrode decreases. To enhance the measurement sensitivity while reducing the electrode size, in this study, microelectrodes employing a nanoporous structure were fabricated and characterized by using electrical impedance spectroscopy. We made the highly ordered honeycomb nanoporous structure of Anodic Aluminum Oxide (AAO) by electrochemical anodizing and formed Au layer on the surface of AAO (Au/AAO) by electroless Au plating method. The electrical characteristics of the fabricated Au/AAO electrodes were evaluated by using de Levie's model derived for the pore electrodes. As a result, the interfacial electrode impedance of the fabricated Au/AAO electrodes was 2-3 order lower than the value of the planar electrodes at frequencies below 1 kHz. It implies this nanoporous electrode could be directly applied to label free detection of biomaterials.

Silicon–Nitride-Passivated Bottom-Up Single-Electron Transistors

We report the elaboration of SiNx-passivated chemically assembled single-electron transistors (SETs) by bottom-up processes involving electroless Au plating and the chemisorption of Au nanoparticles. With a Au top-gate electrode, the SiNx-passivated SETs showed a clear Coulomb diamond at 9 K and the top-gate capacitance was 17 times larger than the side-gate capacitance. Moreover, Coulomb oscillation and the Coulomb diamond were observed even at 160 K. Thus, planar technology is applicable to chemically assembled SETs.

Electroless Nickel and Au Plated Silver LTCC Solution for Advanced Hermetic Packages

Low Temperature Cofired Ceramics (LTCC) for military and medical applications requires high reliability interconnects that have been traditionally met using cermet Au metallization But due to the rising cost of Au, it has become cost prohibitive in some applications to tier 1 defense contractors. The utilization of Silver cermet metallization reduces the costs of LTCC up to 50%, however requires proper coverage using either a Mixed Metal, or a Nickel (Ni) and Au (Au) Plated surface. Efforts to date on mixed metal solutions with resistive PdAg or PtAg transitions without Kirkendahl voiding have been unreliable for systems requiring post fire metallizations due to voiding at the silver to Au transition. Anaren Ceramics has developed an all Silver LTCC solution that utilizes Electroless Ni and Au (ENiG) plating, lowering the cost of entry for LTCC users up to 50%. Anaren Ceramics has developed a proprietary plating process for the DuPont 951 LTCC [1] tape material and silver metallization which meet the needs of high reliability, high cavity count LTCC packages that are fully solderable using PbSn, or AuSn materials for hermetic applications. The Anaren Ceramics solution meets Mil Std 883 test requirements and this paper will discuss the test results for plated LTCC substrates and AuSn brazed LTCC assemblies that include 350°C Bake Test, Tape Peel, X Ray Inspection, Open Header Leak Rate, Moisture under Bias, Salt Atmosphere, Die Shear, and Wire Bond.

Nanoparticle single-electron transistor with metal-bridged top-gate and nanogap electrodes

Au nanoparticle single-electron transistors with metal-bridged top-gates and nanogap electrodes were fabricated using two consecutive electron beam lithography and electroless Au plating steps. The metal-bridged top-gate electrodes were suspended above electroless Au plated nanogap electrodes. Au nanoparticles (5.2 nm in diameter) were chemisorbed between the nanogap electrodes after top-gate fabrication. Clear Coulomb diamonds were observed at 9 K. The gate capacitance Cg of the top-gate electrodes was 99 zF, which is 10 times larger than that of a similar device with only side-gate electrodes.

Single-Electron Transistor Fabricated by Two Bottom-Up Processes of Electroless Au Plating and Chemisorption of Au Nanoparticle

Coulomb diamonds were clearly observed on single-electron transistors (SETs) fabricated by bottom-up processes of electroless plating of Au nanogap electrodes and chemisorption of a Au nanoparticle at 80 K. In the drain current–drain voltage characteristics, Coulomb staircases were modulated by the side gate voltage. Tunneling resistances and source/drain/gate capacitances of the SET were evaluated by fitting the theoretical Coulomb staircase determined on the basis of the full orthodox theory in a double-barrier tunneling junction to the experimental results of Coulomb blockade under the application of side gate voltages. The theoretical results for the Coulomb diamond are in good agreement with the experimental results.

Toward metal-organic insulator-semiconductor solar cells, based on molecular monolayer self-assembly on n-Si

Alkyl chain molecules on n-Si were used to test the concept of hybrid metal-organic insulator-semiconductor (MOIS) solar cells. Test structures were made by binding alkyl chain molecules via Si–O–C bonds to oxide-free n-Si surfaces, using self-assembly. With thiol groups at the terminals away from the Si, binding of Au nanoparticles, followed by electroless Au plating yields semitransparent top contacts. First cells give, under 25 mW/cm2 white light illumination, open-circuit voltage Voc=0.48 V and fill factor FF=0.58. Because with sulfur termination the molecules have a dipole that limits inversion of the Si, we also used methyl-terminated monolayers. Even though then we can work, at this point, only with a Hg top contact, without chemical bond to the molecules, we get, using only radiation (∼AM 1.5) collected around the contact, the expected higher Voc=0.54 V, and respectable 0.8 FF, justifying further MOIS cell development.

Colloidal Crystals of Thermosensitive, Core/Shell Hybrid Microgels

We present the assembly of colloidal crystals composed of various thermoresponsive core/shell microgels and their hybrid microgel counterparts that contain localized Au nanoparticles. To obtain nanostructured microgels, we conducted a three-stage polymerization. First, core microgels composed of cross-linked poly(N-isopropylacrylamide) (pNIPAm) were synthesized by precipitation polymerization. Using these microgels as cores or “seeds”, a copolymer shell of pNIPAm was added to these core particles using a functional comonomer. Finally, a second shell consisting solely of cross-linked pNIPAm was added onto the preformed core/shell microgels by using this seeded polymerization technique. With use of these core/shell/shell microgels as templates, Au nanoparticles were synthesized in situ, using the cationic sites in the inner shell to nucleate particle growth. To control the optical properties of the Au nanoparticles, electroless Au plating was carried out with use of the preformed Au nanoparticles in the microgel as seeds. These hybrid microgels retained their thermoresponsive properties and possessed a high degree of size uniformity as confirmed by dynamic light scattering and were assembled into three-dimensional colloidal crystals by using thermal annealing processes. The resulting colloidal crystals were characterized by optical microscopy and reflectance spectroscopy. This synthetic design for producing distinctive, functional building blocks could be expanded to enable the creation of complex tunable optical materials containing refractive index periodicity on multiple length scales.

Major factors to the solder joint strength of ENIG layer in FC BGA package

Since electroless nickel and immersion gold (ENIG) process was implemented as the surface finish of printed circuit board (PCB) substrate, there have been lots of reports on the brittle fracture between the Ni–P (phosphorous) layer and solder which results in the poor solder joint strength performance. Galvanic corrosion during immersion Au plating process and P-content in Ni–P layer were considered as major factors in the solder joint strength of ENIG layer in this investigation. The attempt to reduce the galvanic corrosion attack in Ni–P layer was made by changing immersion Au plating process to partial electroless Au plating process. Reducing the galvanic corrosion attack was proved to be effective to improve the solder joint strength of ENIG layer. Evaluation of the solder joint performances in variation with the thickness of the Ni layer leads to the conclusion that the thicker Ni layer has the better solder joint strength performances. The result also showed that higher P-content in Ni layer is more favorable to the solder joint strength.

エリソルビン酸を還元剤とする無電解金めっき

The purpose of this investigation was to study electroless Au plating from a sulfite/thiosulfate complex bath (0.015M Na3[Au(SO3)2]+0.1M Na2S2O3+0.4M Na2SO3+0.05M C6H7O6Na+0.18M KOOCCH(OH)CH(OH)COONa) using erythorbic acid as the reducing agent. Deposition rates by autocatalytic reaction and displacement reaction were increased with increasing the concentration of erythorbic acid. The deposition rate by autocatalytic reaction was increased with increasing bath temperature. The deposition rate by displacement reaction was suppressed by the addition of benzotriazole (BTA), di-sodium ethylenediaminetetraacetate (EDTA) and ethylenediamine (en). Electroless Au film which shows a good characteristics in the solder joint strength was obtained from a bath containing BTA, EDTA and en.

Comparison of Lead-Free Solder Joints Made by Immersion Gold Plating with Those Produced by Autocatalytic Electroless Gold Plating

Electroless Ni/Au plating is presently in use with high-density Jisso technology in the manufacture of electrical appliances. Electroless Ni/Au plating is said to be less satisfactory than conventional electrolytic plating with respect to the quality of solder joints and lead-free solder in particular. The reason for this is considered the P-rich layer which forms at the interface of solder bulk and Ni layer but this has yet to be fully confirmed.Solder joints made by electroless Ni/Au plating and Sn–3 mass%Ag–0.5 mass%Cu lead-free solder balls were examined here for reliability assessment under high temperature storage, using an electroless Ni/Au layer made by autocatalytical deposition and another made by immersion Au plating. Interfacial structure and solder pull strength data for the two layers were compared as basis for this assessment and confirm if solder joints made by electrolytic plating is actually superior.At the interface of both layers, cavity formation was found to have occurred by Ni corrosion during Au plating and the number of which appeared to be a factor determining solder joint reliability. Electrolytic Au plating not accompanied by Ni corrosion should provide solder joints with reliability exceeding that by electroless Au plating.

Influence of an Immersion Gold Plating Layer on Reliability of a Lead-Free Solder Joint

Electroless Ni/Au plating is often performed on a surface of a Cu pad to improve the wettability of lead-free solders on such a pad. Generally, electroless Au plating is performed by an immersion plating method. Since a substitution reaction of Ni and Au occurs selectively on the surface of a Ni layer in immersion plating, the Au layer does not uniformly form on the Ni layer and microvoids or microcracks easily form at the Ni/Au interface. Such defects induce void formation at the joint interface in soldering, and consequently degrade the reliability of the lead-free solder joint. In this study, the influences of immersion plating time on microvoid formation at the joint interface and the reliability of a solder ball joint with a Sn-3 mass%Ag-0.5 mass%Cu lead-free solder were investigated.

An 0.1-μm voidless double-deck-shaped (DDS) gate HJFET with reduced gate-fringing-capacitance

This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-/spl mu/m heterojunction FETs (HJFETs) which have about half the external gate fringing capacitance (C/sub f//sup ext/) of conventional T-shaped gate HJFET's. By introducing a T-shaped SiO/sub 2/-opening technique based on two-step dry-etching with W-film masks, we fabricated 0.1-/spl mu/m gate-openings which were suitable for reducing the C/sub f//sup ext/ and filling gate-metals with voidless. The fine gate-openings are completely filled with refractory WSi/Ti/Pt/Au gate-metal by using WSi-collimated sputtering and electroless Au-plating, resulting in high performance 0.1-/spl mu/m DDS gate HJFETs are fabricated. The 0.1-/spl mu/m n-Al/sub 0.2/Ga/sub 0.8/As/i-In/sub 0.15/Ga/sub 0.85/As pseudomorphic DDS gate HJFETs exhibited an excellent V/sub th/ standard-deviation (/spl sigma/V/sub th/) of 39 mV because dry-etching techniques were used in all etching-processes. Also, an HJFET covered with SiO/sub 2/ passivation film had very high performance with an f/sub T/ of 120 GHz and an f/sub max/ of 165 GHz, due to the low C/sub f//sup ext/ with the DDS gate structure. In addition, a high f/sub T/ of 151 GHz and an f/sub max/ of 186 GHz were obtained without a SiO/sub 2/ passivation film. This fabrication technology shows great promise for high-speed IC applications.