Electrostatic Discharge Protection Devices Research Articles

3-D TCAD Methodology for Simulating Double-Hysteresis Filamentary I–V Behavior and Holding Current in ESD Protection SCRs

Current filament (CF)-related double-hysteresis I-V behavior and holding current, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD</sub> ,are analyzed using experiments and 3-D technology computer-aided design (TCAD) simulation in silicon-controlled rectifiers (SCR) for system-level electrostatic discharge (ESD) protection. Our 3-D TCAD methodology uses up and down quasi-dc current sweeps to reveal a memory effect in the current density distribution along the device width. I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> is related to the smallest possible CF where the self-sustaining SCR action takes place during down current sweep. I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD</sub> exhibits a nontrivial dependence on device width, depending on whether a CF is created or not. Analyzing devices of different layouts shows that I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> values determined from experiments and 3-D TCAD are almost layout-independent and substantially lower than those evaluated from 2-D TCAD. I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> calculated by 3-D TCAD in edge-terminated devices is higher than that in 3-D structures obtained from simple width-extended 2-D doping profiles. The use of latter devices, thus, simplifies the 3-D TCAD I- V analysis and provides a safe margin for I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> prediction. The work is relevant for designing the latch-up immunity of ESD protection devices, and it also shows that conventional 2-D TCAD can provide unwanted overestimation of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD</sub> .

Design of a Robust ESD Protection Device using 6H-SiC Nano-Scale GGNMOS

With the continuous shrinking of the technological nodes and the introduction of new device concepts and materials, integrated circuits (IC) are becoming more vulnerable to electrostatic discharge (ESD) induced failures which is one of the major concerns in designing robust ICs. Therefore, to improve the reliability of the ICs against ESD induced failures, extensive research efforts are being conducted. In this paper, we have presented a 6H-SiC based nano-scale grounded-gate NMOS (ggNMOS) ESD protection device and compared the results with the 3C-SiC-based ggNMOS. To design a robust ESD protection device, some critical device parameters, such as substrate doping concentration, source/drain doping concentration, drain to substrate contact spacing, and substrate contact resistance should be optimized. The ESD protection characteristics can be improved by utilizing the near punch-through effect. It was found that the trigger voltage and hold voltage are higher in 6H-SiC than the 3C-SiC having identical device parameters. 6H-SiC shows better voltage clamping performance as the turn-on resistance of 6H-SiC is smaller compared to the 3C-SiC material. Therefore, the results show that 6H-SiC has a better performance compared to 3C-SiC and due to its higher bandgap, and can be used as a good ESD protection device. All the simulations are carried out using the Silvaco ATLAS device simulator.

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

Rapid characterization of efficient system level ESD protection strategy using coupling transfer function

This study details a new technique for the fast and efficient design and analysis of system level electrostatic discharge (ESD) protection strategy using developed coupling transfer impedance function. The transfer coupling characteristics from the zapping point to the victim location on a DUT can be computed using coupling transfer gain function. Subsequently, it is integrated with an ESD current source in a SPICE type circuit simulator for the fast and efficient analysis of induced ESD coupling noise and the design of the appropriate ESD protection scheme with the suitable choice of ESD protection device (diodes, SCR, GGNMOS, GCNMOS etc.). The study discusses the different protection schemes i.e. primary, secondary and double ESD protections, and the effect of the selected diode types and ESD stressing levels on the employed protection strategy. The proof-of-concept is validated through the rapid design of suitable system level ESD protection strategy for a microstrip-line PCB, high-speed mobile device memory module, and a portable notebook motherboard.

Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures* *Project supported by the National Natural Science Foundation of China (Grant No. 61804168).

Trigger characteristics of electrostatic discharge (ESD) protecting devices operating under various ambient temperatures ranging from 30 °C to 195 °C are investigated. The studied ESD protecting devices are the H-gate NMOS transistors fabricated witha 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. The measurements are conducted by using a transmission line pulse (TLP) test system. The different temperature-dependent trigger characteristics of grounded-gate (GGNMOS) mode and the gate-triggered (GTNMOS) mode are analyzed in detail. The underlying physical mechanisms related to the effect of temperature on the first breakdown voltage V T1 are investigated through the assist of technology computer-aided design (TCAD) simulation.

4H-SiC-Based ESD Protection Design With Optimization of Segmented LIGBT for High-Voltage Applications

4H-SiC is a wide-bandgap material that exhibits excellent high-temperature conductivity and high operating voltage. These characteristics can provide high electrostatic discharge (ESD) robustness in high voltage applications. However, a considerably wide range of snapback phenomena is triggered for 4H-SiC-based ESD protection devices owing to a high critical electric field. In this study, an ESD protection device based on a lateral insulated-gate bipolar transistor (LIGBT) with a new structure that creates an internal silicon-controlled rectifier (SCR) path is proposed. The proposed ESD protection device minimizes the effective base region of the NPN parasitic bipolar transistor to the gate length based on the internal SCR operation of the LIGBT. It also adjusts the emitter injection efficiency of the PNP parasitic bipolar transistor by introducing a segment topology and inserting an additional implant area. Consequently, the proposed ESD protection device significantly improves the wide range of snapback phenomena occurring in the 4H-SiC materials. A conventional SCR, the LIGBT, and the proposed protection device were fabricated using the 4H-SiC process under the same condition, and their electrical characteristics were comparatively analyzed using a transmission-line pulse system. Moreover, its high-temperature reliability was evaluated at 300–500 K to examine the compatibility with 4H-SiC devices and circuits that require a relatively high-temperature operation.

The Design Of Broadband I/O Circuits [The Analog Mind

The transport of high-speed data to and from chips requires input-output (I/O) interfaces with a commensurately wide bandwidth. In addition to the parasitic capacitances that the output driver in a transmitter (TX) and the input stage in a receiver (RX) present to the signal path, both interfaces must also deal with the capacitances associated with electrostatic discharge (ESD) protection devices. The I/O design thus becomes increasingly more challenging as greater speeds are sought. In this article, we design I/O circuits for a data rate of 40 Gb/s with a singleended voltage swing of 0.5 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> while focusing on the use of T-coils. The reader is referred to [1]-[5] for background information.

This paper analyzes the operation mechanism of integrated circuit electrostatic discharge (ESD) protection device

Electrostatic discharge, as a common natural phenomenon in daily life, seriously threatens the reliability of integrated circuit products. In order to ensure the yield of the chip, the protection circuit on the chip has become an essential and important module in the circuit design. With the continuous development of integrated circuit technology, chips are developing towards the direction of smaller area, faster speed and higher level of integration, while traditional devices such as simple diodes, tubes and SCR on integrated circuit can no longer complete the protection task of chips under advanced technology. Through the research and discussion of this paper, the methods and strategies of electrostatic discharge protection design of integrated circuits and how to choose the best electrostatic discharge protection scheme for different integrated circuits are basically mastered.

Experimental results on diodes and BIMOS ESD devices in 28 nm FD-SOI under TLP & TID radiation

The electrostatic discharge (ESD) protection is a major concern for advanced CMOS technology manufacturing. Several solutions are available on market with efficient robustness and compliant with the ESD window especially in 28 nm FD-SOI technology. In the framework of harsh environment applications and to explore the performance under total ionizing dose (TID) radiation, it is important to investigate ESD protection devices such as gated and STI diodes in hybrid bulk or BIMOS solution in thin silicon film. This study is based on transmission line pulse (TLP) characterization before and after Co60 TID radiation in the range of [25 krad–200 krad]. This dose range is chosen for a first robustness exploration and in link with product applications. Following this analysis, we expect to gain better understanding of robustness and push the final performance of the device. The preliminary results will be useful to give a trend and to improve the device robustness against ESD and TID events and lead to more competitive solutions.

A 4H-SiC MOSFET-Based ESD Protection With Improved Snapback Characteristics for High-Voltage Applications

A novel electrostatic discharge (ESD) protection device based on an n-type metal–oxide–semiconductor field-effect transistor (NMOSFET) with segmented topology was proposed and investigated, considering the material characteristics of 4H-SiC, which is a wide-bandgap material (3.3 eV). ESD phenomena are important in terms of semiconductor reliability, and the benefits of using 4H-SiC as a material can provide robustness and excellent thermal reliability to ESD protection devices. The proposed device improves the wide range of snapback phenomena caused by the high critical electric field (2.4 MV/cm), in comparison to using Si (0.25 MV/cm); it also improves triggering characteristics and provides a high holding voltage. The proposed device and a traditional silicon-controlled rectifier, a gate-grounded-NMOS, and a gate-body floating NMOS were fabricated using the 4H-SiC process. The electrical characteristics of the experimental devices, determined by a transmission-line-pulsing system, were comparatively analyzed. Additionally, this article presents the analysis of the optimization of electrical characteristics according to the critical design variables of the proposed device, stacking for high-voltage applications, and reliability test results for high temperatures (300–500 K).

A Gate-Grounded NMOS-Based Dual-Directional ESD Protection With High Holding Voltage for 12V Application

Dual-direction electrostatic discharge (ESD) protection devices can discharge both positive and negative ESD surges, owing to their excellent area efficiency. This study proposes a novel dual-direction MOSFET ESD protection device with a high holding voltage. Most existing dual-direction ESD protection devices are based on silicon-controlled rectifiers (SCR). Among them, the low triggering dual-directional SCR (LTDDSCR) has good trigger characteristics, but with low holding voltage. In contrast, the proposed high-holding-voltage dual-direction NMOS (HHDDNMOS) operates using two NPN parasitic bipolar transistors connected to the ESD discharge path and has a very high holding voltage and excellent snapback characteristics. The electrical and dual-directional characteristics of HHDDNMOS were analyzed using the transmission-line -pulsing system, and the latch-up immunity was verified by conducting transient-induced latch-up tests using the 0.18-μm BCD process.

New embedded DDSCR structure with high holding voltage and high robustness for 12-V applications**Project supported by the National Natural Science Foundation of China (Grant Nos. 61704145, 61774129, and 61827812), the Natural Science Foundation of Hunan Province, China (Grant No. 2019JJ50609), and the Key Technology Program of Changsha City, China (Grant No. kq1902042).

A new dual directional silicon-controlled rectifier based electrostatic discharge (ESD) protection device suitable for 12-V applications is proposed in this paper. The proposed device (NPEMDDSCR) is based on the embedded DDSCR (EMDDSCR) structure, in which the P+ electrode and P+ injection are removed from the inner finger. Compared with the conventional modified DDSCR (MDDSCR), its high holding voltage meets the requirements for applications. Compared with the embedded DDSCR (EMDDSCR), it has good conduction uniformity. The MDDSCR, EMDDSCR, and NPEMDDSCR are fabricated with an identical width in a 0.5-μm CDMOS process. In order to verify and predict the characteristics of the proposed ESD protection device, a transmission line pulse (TLP) testing system and a two-dimensional device simulation platform are used in this work. The measurements demonstrate that the NPEMDDSCR provides improved reliability and higher area efficiency for 12 V or similar applications. The measurement results also show that the NPEMDDSCR provides higher robustness and better latch-up immunity capability.

Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High- Speed Digital Application in 16-nm FinFET Process

The FinFET architecture has widely been used in the digital circuit application, due to the good short channel effect control and driving current boost. However, the worse thermal dispassion and smaller effective silicon volume would cause the significant impacts during the circuits under electrostatic discharge (ESD) event. Thus, the ESD protection device should be installed into the high-speed digital circuit to enhance the ESD robustness. To avoid the effect of circuit performance, the parasitic capacitance of ESD device must be as low as possible. In this article, two types of Fin-diode-triggered rotated silicon-controlled rectifier (SCR) with dual ESD current path have been proposed and verified in a 16-nm FinFET CMOS process. The proposed devices have better current-handling capability, sufficiently low parasitic, compact layout area, and low leakage current.

RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process

In order to meet the requirement of ultrahigh-speed, low latency, and wide bandwidth (BW) in the next 5G mobile network and internet of things (IoT) applications, the parasitic capacitance specification of electrostatic discharge (ESD) protection devices should become much stricter. Reducing the capacitance always degrades the ESD performance in terms of shrinking the size of the ESD protection device. The distributed ESD protection network is one of the solutions which mitigates the capacitance issue and provides a broadband design. However, while the ESD devices are put under the I/O pad in the distributed ESD protection network, back-end-of-line (BEOL) capacitance starts to play an important role in the advanced 28-nm CMOS process. Therefore, a tapered metal structure is proposed to significantly reduce 30% BEOL capacitance of the ESD device, which can gain a 2.8-GHz increase in the operational BW in the distributed network. Meanwhile, it can enhance the human-body-model (HBM) level up to 16% higher than the original layout style under the same front-end-of-line (FEOL) layout size.

The impact of radiation and temperature effects on dual-direction SCR devices for on-chip ESD protections

The reliability issues of integrated circuits are attracting more attention, especially in extreme environments like radiation and elevated temperature conditions. The impact of ionizing radiation and temperature effects on the electrostatic discharge (ESD) protection devices should not be negligible. In this paper, A low-voltage dual-direction silicon controlled rectifier (DDSCR) and a high-voltage DDSCR based on laterally diffused metal oxide semiconductor are chosen and fabricated in a 5 V/18 V Bipolar-CMOS-DMOS process. To study the combined effects of ESD and total-ionizing dose, transmission line pulse (TLP) measurements are conducted right after exposure to 60Co gamma-ray up to 200 krad(Si). Besides, the TLP tests are performed at different temperatures ranging from 300 to 400 K to show the impact of elevated temperature on ESD devices. In the meanwhile, the physical mechanisms of the synergistic effects are investigated by means of three-dimensional (3D) TCAD simulations.

A New SCR Structure With High Holding Voltage and Low ON-Resistance for 5-V Applications

This article proposes a new silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection device suitable for 5-V applications. The proposed ESD protection device has an additional n-p-n parasitic bipolar transistor that provides an extremely short ESD discharge path. Compared with the conventional Low-Voltage-Trigger SCR (LVTSCR) and Low-Ron SCR (LRSCR), it has excellent ON-resistance and improved reverse characteristics. Furthermore, it has structurally enhanced trigger voltage and holding voltage characteristics. A conventional LVTSCR, LRSCR, and the proposed ESD protection device were fabricated with the same width using a 0.18- $\mu \text{m}$ bipolar CMOS DMOS (BCD) process to verify the improvement in electrical characteristics and current driving capability of the new device. Transmission line pulsing (TLP) and a hot chuck control system were used to measure and compare the latch-up, electrical characteristics, and temperature reliability of the three devices. The measurements demonstrate that the proposed ESD protection device provides improved reliability and higher area efficiency for 5 V or similar applications.

VO2 Switch for Electrostatic Discharge Protection

On-chip protection from electrostatic discharge (ESD) and electrical overstress (EOS) is a continuous challenge in the semiconductor industry, requiring significant design costs and die space. Insulator-metal transition (IMT) materials like vanadium dioxide (VO2) could be used as bidirectional, compact voltage snapback devices for ESD protection that are not required to be in the front-end silicon. However, the reliability and response of these materials to ESD is not yet well studied. Here, we perform transmission line pulse (TLP) tests on thin film (50– 150 nm) VO2 devices. These can repeatedly sustain high currents in their metallic state, but still return to insulating once an ESD event is over. Devices with widths from 5 to 50 $\mu \text{m}$ can carry a maximum current ( ${I} _{{\text {t}2}}$ ) from ~1 to over 10 A, equivalent to ~1 to 15 kV of ESD protection. Furthermore, the snapback voltage can be engineered by varying the device length. These results suggest that IMT materials could be promising for use in on-chip ESD/EOS protection.

Compact ESD Protection Cell for Multi-Band Millimeter-Wave Applications

A compact electrostatic discharge (ESD) protection cell is proposed for multi-band millimeter-wave (MMW) circuits in nanoscale CMOS technology. The proposed ESD protection cell consists of a silicon-controlled rectifier (SCR) and a diode as the main ESD protection devices, and an inductor in this cell is divided into several sections to resonate at multifrequencies. The proposed design has been demonstrated for 28- and 67-GHz applications. The measurement results show that the proposed design exhibits lower loss at the specified frequency bands, higher ESD robustness, and sufficiently small layout area. Therefore, the novel compact ESD protection cell will be better for multi-band MMW applications in CMOS technology.

ESD Protection Design for Open-Drain Power Amplifier in CMOS Technology

The on-chip electrostatic discharge (ESD) protection device for radio-frequency (RF) power amplifier (PA) with open-drain structure is studied in this work. The conventional ESD protection device of stacked diodes and the proposed ESD protection device of stacked diodes with embedded silicon-controlled rectifiers (SCRs) are compared in silicon and applied to the 2.4GHz PAs. The proposed ESD protection device has the advantages including higher ESD-current-handling ability, lower ESD-clamping voltage, and sufficiently low parasitic capacitance. Besides, the proposed ESD protection device does not degrade the PA performances. Therefore, the proposed ESD protection device of stacked diodes with embedded SCRs is more suitable for CMOS PAs.

Drain-Extended FinFET With Embedded SCR (DeFinFET-SCR) for High-Voltage ESD Protection and Self-Protected Designs

This article presents device design insights and design challenges for drain-extended FinFET devices with embedded silicon-controlled rectifier (SCR) (DeFinFET-SCR), which can be used as an electrostatic discharge (ESD) protection device and a self-protected high-voltage switch/driver for system-on-chip applications. The tradeoff between maximizing ESD robustness without hindering the transistor’s operation is discussed in detail. An interplay between parasitic p-n-p turn-on and space charge modulation (SCM) is revealed, which strongly influences the strength of parasitic SCR and its turn-on efficiency during ESD and DC operations. Developed physical insights show that engineering p-n-p turn-on and onset of SCM are the key to maximize ESD robustness without causing early SCR turn-on during transistor operation. Based on new findings and developed physical insights, design guidelines have been derived for ESD robust DeFinFET-SCR.