EEPROM Research Articles

Memory characteristics of Au nanocrystals embedded in metal–oxide–semiconductor structure by using atomic-layer-deposited Al2O3 as control oxide

The nonvolatile memory characteristics of metal–oxide–semiconductor (MOS) structures containing Au nanocrystals in the Al2O3/SiO2 matrix were studied. In this work, we have demonstrated that the use of Al2O3 as control oxide prepared by atomic-layer-deposition enhances the erase speed of the MOS capacitors. A giant capacitance–voltage hysteresis loop and a very short erase time which is lower than 1 ms can be obtained. Compared with the conventional floating-gate electrically erasable programmable read-only memories, the erase speed was promoted drastically. In addition, very low leakage current and large turn-around voltage resulting from electrons or holes stored in the Au nanocrystals were found in the current–voltage relation of the MOS capacitors.

DEVELOPMENT OF A PORTABLE SYSTEM FOR CHECKING RADIOACTIVE SOURCES USING LONG WAVE RADIO FREQUENCY IDENTIFICATION

A portable system for automatically checking radioactive sources stored in lead containers at low temperatures was developed in order to prevent the discharging of orphan sources and contaminated materials from a controlled area to the general public. A radio frequency identification (RFID) system using a long wave in a frequency range of 125 kHz was composed of identification tags, a reader, a notebook computer, and software. ID tags without batteries were devised by using integrated circuits with an electrically erasable programmable read-only memory of 250 bytes and antennas. This software consisted of operating and maintenance functions. The read range of the ID tags was adjusted to around 5 cm in order to avoid accidental contamination and for discriminating the multiple sources. A water layer of 6.9 cm had no influence on communication between the ID tags and the reader. The data of the ID tags stored at +4, -20, and -80 degrees C were precisely read 4 mo later. The influence of lead was completely removed by separating the ID tags more than 1.6 cm from the lead. A reader can exactly identify the data of the ID tags within 6.0 cm at a velocity less than 9.0 cm s(-1). Performance of the software was verified using mock data. Nine lists concerning registered, disposed, and missing sources, etc., were displayed on the computer monitor and printed out. An RFID system using long waves proved to be applicable for routinely checking radioactive sources.

Novel Single Polysilicon EEPROM Cell With Dual Work Function Floating Gate

A novel single polysilicon electrically erasable programmable read-only memory cell with dual work function floating-gate (DWFG) structure is presented in this letter. The floating gate of the proposed DWFG cell is doped with p+ on the source side and n+ on the drain side. For DWFG devices, the floating gate on the source side has a higher work function than that on the drain side. The work function difference and the intrinsic doped region at the middle of the floating-gate affect the channel potential distribution and generate a peak lateral electric field inside the channel, improving the channel's hot electron programming characteristics. The experimental results show that the proposed DWFG cell gives faster programming speeds and program operation at lower voltage than conventional cells

Enhanced Planar Poly-Si TFT EEPROM Cell for System on Panel Applications

In this work an enhanced electrically erasable programmable read-only memory (EEPROM) device comprised of twin low-temperature poly-Si thin-film transistors (TFTs) was fabricated for potential application to system-on-panel technology. Also, two kinds of memory devices with different overlap areas were developed to investigate the gate-coupling effect. The memory window of 4.8 and 4 V can be obtained at a programming voltage of 18 V, separately, for the fully overlapped EEPROM and the one with a 1 μm length overlap between the gate and source/drain. The excellent memory characteristics of the fully overlapped TFT EEPROM cell are attributed to the enhanced gate-coupling ratio by maximizing the overlap coverage between the gate electrode and the source/drain regions.

Investigation of Drain Disturb in SONOS Flash EEPROMs

The mechanism of drain disturb is studied in silicon-oxide-nitride-oxide-silicon Flash electrically erasable programmable read-only memory cells. It is shown that disturb is a serious problem in programmed cells and is caused by injection of hot holes from substrate into the oxide/nitride/oxide stack. The origin of these holes is identified by analyzing the influence of halo doping, channel doping, and channel length scaling on drain disturb. Band-to-band tunneling at the drain junction is normally the dominant source of these holes. It is also shown that holes generated out of impact ionization of channel electrons become dominant in cells with high channel leakage (especially at lower channel lengths). Finally, the effect of repeated program/erase cycling on drain disturb is studied. Drain disturb becomes less severe with cycling, the reasons for which are determined using gate-induced drain leakage measurements and device simulations

Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells

The erase threshold-voltage (VT) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into VT transient for simulating erase VT dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller VT dispersion, compared with SA-STI. The VT dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed VT distribution, calling for examination of additional process and cell parameters

Silicon photonic read-only memory

In this paper, a CMOS-compatible in-plane micrometer-size optically readable nonvolatile-memory device is proposed and analyzed. It consists of an electrically erasable programmable read-only memory (EEPROM) integrated on a high-index-contrast silicon-on-insulator (SOI) rib waveguide. Our calculations indicate that variations on the order of 10/sup -4/ of the waveguide effective refractive index can be achieved for the typical values of stored charge (on the order of 10/sup 12/ q/sub e//cm/sup 2/) on a floating gate. A microring resonator, based on such waveguide, efficiently converts the calculated index variations into strong intensity variations. This photonic structure can be used to create nonvolatile optically readable memory states in a photonic device [photonic EEPROM (PEEPROM)] with an ultrafast read time. A microring-resonator intensity-modulator PEEPROM is predicted to exhibit a modulation depth of 91% (10.4 dB) between the uncharged and charged (3.75/spl times/10/sup 12/ q/sub e//cm/sup 2/) states. The read time of the device is only 9 ps, which is at least two orders of magnitude shorter than that of a standard two-transistor electrically readable EEPROM.

Suppression of Oxide Encroachment into Floating Gate by Shallow Trench Isolation Recess in an Electrically Erasable Programmable Read Only Memory Cell

In this paper, we investigate the effects of the oxide recess in shallow trench isolation (STI) on the characteristics of electrically erasable programmable read only memory (EEPROM) cell with in situ-doped floating gate. It is found that the distribution of the program threshold voltage is improved with increasing of the oxide recess in STI. Transmission electron microscopy analysis shows that the oxide recess in STI results in the decrease of oxide thickness at the edge of STI and in the center of tunnel oxide. Also, it is observed that erase cell current is increased about 11% with oxide recess of and 21% with oxide recess of , respectively. Endurance measurements in the EERPROM cell reveal that both electron and charge generation increase with increasing recess depth when the cycling time exceeds about .

Effect of H 2O evolving from TEOS based SiO 2 film on the EEPROM cell characteristic

In this paper, we investigate the effect of water (H 2O) molecules evolving from silicon dioxide (SiO 2) film deposited by low pressure chemical vapor deposition (LPCVD) at 670 °C on the transistor characteristic of an electrically erasable programmable read only memory (EEPROM) cell. Fourier Transform Infra red (FT-IR) analysis reveals that H 2O is captured during film deposition and diffused to silicon surface during high thermal processing. The diffused H 2O molecules lower threshold voltage ( V t) of cell transistor and, thus, leakage current of the cell transistor is increased. In erased cell, V t lowering is 0.25 V in which it increases leakage current of cell transistor from 1 to 100 pA. This results in the lowering of high voltage margin of a 512 Kb EEPROM from 2.8 to 2.6 V at 85 °C.

High-performance single polysilicon EEPROM with stacked MIM capacitor

High-performance single polysilicon electrically erasable programmable read-only memories (EEPROMs) with stacked metal-insulator-metal capacitor as a control gate are investigated. The thickness of the tunnel oxide and the length of the floating gate channel of the fabricated devices were 52 /spl Aring/ and 0.24 /spl mu/m, respectively. The effective control gate coupling ratio of the proposed EEPROM cell was higher than that of cells with n-well control gate because of the absence of depletion capacitance in the n-well silicon region. The experimental results showed that the program speed of the proposed cells were faster than those of the conventional n-well control gate cells. In addition, the proposed cells had threshold voltage shifts of 3.5 V between program and erase states. Furthermore, there were threshold voltage shifts of 3.0 V without degradation of the read currents after 1000 program/erase cycles.

Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injection

The lateral profile of trapped charge in a silicon-oxide-nitride-oxide-silicon (SONOS) electrically erasable programmable read-only memory programmed using channel-hot-electron injection is determined using current-voltage (I/sub D/-V/sub G/) measurements along with two-dimensional device simulations and is verified using gate-induced-drain-leakage measurements, charge-pumping (CP) measurements, and Monte Carlo simulations. An iterative procedure is used to match simulated I/sub D/-V/sub G/ characteristics with experimental I/sub D/-V/sub G/ characteristics at different stages of programming, by sequentially increasing the trapped electron charge in simulations. Fresh cells are found to contain a high laterally nonuniform trapped charge, which (along with large electron injection during the program) make the conventional CP techniques inadequate for extracting the charge profile. This charge results in a nonmonotonous variation of threshold and flat-band voltages along the channel and makes it impossible to simultaneously determine interface and trapped charge profiles using CP alone. The CP technique is modified for application to SONOS cells and is used to verify the charge profile obtained using I/sub D/-V/sub G/ and to estimate the interface degradation. This paper enhances the study presented in our earlier work.

Metal nano-floating gate memory devices fabricated at low temperature

In this communication, we report on the realization of low-temperature processed Electrically Erasable Programmable Read-Only Memory (EEPROM) like device with embedded gold nanoparticles. The realization is based on the fabrication of a V-groove SiGe Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the functionalization of a gate oxide followed by self-assembly of gold nanoparticles and finally, the deposition of an organic insulator by Langmuir–Blodgett (LB) technique. Such structures were processed at a temperature lower than 400 °C. The electrical characteristics of the final hybrid Metal Insulator Semiconductor FET (MISFET) memory cells were evaluated in terms of memory window and program/erase voltage pulses. A model describing the memory characteristics, based on the electronic properties of the gate stack materials, is presented.

Using Soft Secondary Electron Programming to Reduce Drain Disturb in Floating-Gate NOR Flash EEPROMs

A novel concept of soft secondary electron programming (SSEP) is introduced and shown to be a promising programming scheme for scaled NOR flash electrically erasable programmable read-only memories. Although the mechanism is similar to that of the channel-initiated secondary electron (CHISEL) programming, SSEP uses an optimum substrate bias that results in a lower drain disturb compared with both channel hot electron (CHE) and conventional CHISEL programming schemes. The concept behind minimizing drain disturb is discussed. SSEP is shown to give faster programming and lower disturb than CHE at all operating conditions, as well as better program/disturb margin compared with conventional CHISEL programming at similar program speed or disturb time. The effect of repeated program/erase cycling using SSEP is compared against CHE and CHISEL cycling.

Microdosimetry of the ultraviolet erasable programmable read-only memory experiment on the microelectronics and photonics test bed: recent advances in small-volume analysis

A commercial ultraviolet erasable programmable read-only memory (UVPROM) was used to demonstrate a dosimetry technique for both ground and space applications. An equivalent amount of UV to reproduce the same amount of erasure was used to calibrate dose. The new method of readout, unlike other methods, does not require the evidence of exposure to be destroyed in the course of a measurement. It requires power only during readout. Results from an experiment using this technique aboard the Microelectronics and Photonics Test Bed (MPTB) satellite are discussed. Application of Extreme Value Theory is used to analyze whether early failures in the device were statistically feasible or more likely due to large, rare energy depositions. A new dosimeter approach using a change injection method that will eliminate the need for UV as a metric is also presented as well new experiments for the devices under test aboard MPTB.

Fast and sensitive electret polymer characterization by extended floating gate MOSFET

A new characterization method for charge conditions in electret polymer films is proposed. This method uses the change of the threshold voltage in an EEPROM (electrically erasable and programmable read-only memory) device to evaluate the effective charge density in electret. The EEPROM device has an extended floating gate that is capacitively coupled to a sensing gate in direct contact with the electret polymer film. It also has a control gate similar to that in the conventional EEPROM device driven by test signals. By the total capacitive loads and effective charges seen on the floating gate, the surface potential of the transistor channel in the subthreshold region is a linear function of effective electret charge density. Representative measurements with several electret charging conditions, such as photo poling and mechano poling are provided. With the bandwidth of the EEPROM device typically much higher than 1 kHz, real-time charging characteristics with sub-millisecond resolution can be obtained.

Deterioration of stressed oxides: Application to the prediction of a non-volatile memory cell endurance

This paper investigates a new way of predicting an electrically erasable programmable read only memory (EEPROM) cell’s endurance without stressing the cell itself. Tunnel equivalent capacitors, formed by silicon dioxide thermally grown on N + type Si substrates and then covered with polycrystalline silicon, undergo dynamic stress made up of one million rectangular pulses. Then, Fowler–Nordheim parameters α and β are obtained after a few numbers of applied pulses. EEPROM model simulation with extracted α and β shows closure of programming window as number of cycles varies from 1 to 10 6. Comparison between simulated closure of programming window and measured closure of programming window from EEPROM endurance tests shows that simulated programming window closure is greater, especially at smaller numbers of write/erase cycles. This greater severity is attributed to tunnel oxide degradation due to additional stress caused by Fowler–Nordheim current measurement. We also compare the deterioration of the tunnel oxide caused by successive writings and the deterioration caused by successive erasings, which are found to be of the same amount.

Non-volatile memory cell design: Coupling ratio impact on tunnel oxide reliability

In a previous work, using a physical compact model to predict cell operation, we have shown a paradoxical impact on the evolution of the electrical field through the thin tunnel oxide with regard to the coupling ratio. It seems paradoxical to obtain an increase of electric field through the tunnel oxide when using decreasing applied voltage by an increased of the coupling ratio. In this paper we confirm these predictions by an endurance test on electrical erasable programmable read only memory (EEPROM) samples. These samples, provided by ST Microelectronics, were designed to reach different coupling ratio, by adjusting the capacitive areas of the cell. We adjusted the length and the width of the sense transistor, by this way, we changed only the tunnel area and we keep the inter-poly capacitance constant. The degradation increases while the applied voltage decreases that is to say the degradation increases with the coupling ratio, and this degradation is clearly related to the electrical tunnel field and to the surface charge density.

Algorithms and data structures for flash memories

Flash memory is a type of electrically-erasable programmable read-only memory (EEPROM). Because flash memories are nonvolatile and relatively dense, they are now used to store files and other persistent objects in handheld computers, mobile phones, digital cameras, portable music players, and many other computer systems in which magnetic disks are inappropriate. Flash, like earlier EEPROM devices, suffers from two limitations. First, bits can only be cleared by erasing a large block of memory. Second, each block can only sustain a limited number of erasures, after which it can no longer reliably store data. Due to these limitations, sophisticated data structures and algorithms are required to effectively use flash memories. These algorithms and data structures support efficient not-in-place updates of data, reduce the number of erasures, and level the wear of the blocks in the device. This survey presents these algorithms and data structures, many of which have only been described in patents until now.

EEPROM programming window changes with operating temperature

This paper is devoted to the understanding of Electrically Erasable Programmable Read Only Memory (EEPROM) programming window (PW) changes with operating temperature. First a theoretical analysis is carried out, and two main contributions to the PW change are identified: change of the sense transistor characteristics and variation of the FN (Fowler–Nordheim) injection mechanism. An experimental study is then conducted on samples with various size (0.8 and 19 360 μm 2) and coupling coefficients (0.45, 0.62 and 0.71), for temperatures in the range 25–200 °C. Whereas the results concerning the erased mode are reproducible and quantitatively explained by the model, data relative to the written state of real size cells features an irreproducible behavior which was not elucidated.

Hot-electron injection in stacked-gate metal-oxide-semiconductor field-effect transistors

Hot-electron injection in high dielectric constant stacked-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) is studied theoretically by combining a hybrid Monte Carlo/iterative simulation of hot carrier transport with a transfer-matrix calculation of the transmission probability through the insulators. It is shown that the reduced potential barrier between the silicon and the high dielectric constant material results in high gate currents in short channel MOSFETs even at low drain voltages. The structure may therefore find applications in electrically erasable programmable read-only memory devices.