Electrical Fault Isolation Research Articles

The EDFAS FA Technology Roadmap—Die-Level Roadmap Council (DLRC)

Abstract The EDFAS Die-Level Roadmap Committee was formed to identify forthcoming challenges related to electrical fault isolation within the next five years and collaborate with various stakeholders, including industry, academia, and tool vendors, to devise practical solutions. To that end, the team has pinpointed five critical areas of focus: (1) laser-based, photon emission, and thermal; (2) 2D/2.5D/3D packaging; (3) product yield, test, and diagnostics; (4) general (leading edge technologies); and (5) system level, analog/RF, and digital functional.

Dynamic EFI and circuit analysis case studies on integrated circuit buried via void defects

Buried via voids defect beneath the metal layer of an integrated circuit (IC) has always been a challenge to localize. The importance of dynamic electrical fault isolation (EFI) approaches, automated multi-level circuit net trace, and test bench simulation on buried via void localization are discussed in this paper. Three buried via void case studies will be discussed, including a hard functional failure, an ATPG soft failure, and a high dynamic leakage current (IDD) failure.

Cross-sectional nanoprobing sample preparation on sub-micron device with fast laser grooving technique

Cross-sectional sample preparation is one of the most important failure analysis (FA) techniques in the semiconductor industry. It was commonly used for film stack critical dimension measurement, defect identification, electrical fault isolation and etc. However, cross-sectional sample preparation to a specific target location on a sub-micron device is very challenging and time-consuming. This is because of mechanical polishing easily caused metal smear, delamination, film peel-off, micro-cracked and etc. This paper focused on cross-sectional nanoprobing (XNP) sample preparation improvement in quality and quantity. A laser blast to deprocess or create a groove at near to target location before conventional mechanical polishing and focus ion beam (FIB) fine milling. The proposed technique not only reduces the sample preparation time to the sub-micron target location but also prevent mechanical damages that caused by mechanical polishing technique.

Understanding spatial resolution of laser voltage imaging

Laser voltage imaging (LVI) is a commonly used electrical fault isolation technique that is extremely useful in the localization of defects in serial chains and circuits generating specific frequencies within modern integrated circuits. The signals are generated by electro-optic phenomena and the resolution of the tool is therefore constrained by the optical diffraction limit. As such, conventional methods of understanding optical resolution in optical systems such as Rayleigh and Sparrow criteria are currently used to describe the effective resolution. This work formalizes the description of resolution in LVI considering the point spread function of the laser and the electrical circuitry the laser interacts with. Finally, the model is compared with real results across multiple laser wavelengths and is shown to be useful for resolution prediction, determination of optimum probe placement position and predicting the shape of LVI under constrained space conditions.

Embed SRAM IDDOFF fail root cause identification by combination of device analysis and localized circuit analysis

SRAM is most important component in the logic product. The failure analysis on the SRAM is well developed, but the SRAM IDDOFF analysis is still challenging for the FA engineers. The product has passed the functional test when IDDOFF is measured. This will make electrical fault isolation very difficult. It will be easy to verify the IDDOFF leakage at die level, but difficult or impossible to verify the leakage at the transistor level. In this paper, a SRAM IDDOFF failed unit was analyzed and the conventional EMMI method was employed to do the fault isolation. The hotspot was easily found in the SRAM area. The EMMI signal cover the entire SRAM block, which indicates a gross leakage in the SRAM block. Subsequent layer by layer analysis didn't find any abnormality until contact level. Nanoprobing at contact level also shows nothing abnormal. To understand the leakage path, the SRAM circuit was studied under DC bias condition and combined with a cross-section analysis of the structure. Thus, a suspected leakage path was proposed. Based on this suspect the leakage can only be simulated at M1 level, and then the experiment was redesigned at Via1 level. The leakage was successfully verified by the nanoprobing DC measurement at M1 level. Finally, the TEM analysis confirms the root cause for the IDDOFF fail.

Current imaging, EBIC/EBAC, and electrical probing combined for fast and reliable in situ electrical fault isolation

Using a compact nanoprobing setup comprising eight probe tips attached to piezo-driven micromanipulators, various techniques for fault isolation are performed on 28nm samples inside an SEM. The employed techniques include nanoprobing as well as EBAC. The recently implemented Current Imaging technique is used to quickly image large arrays of contacts providing a means of locating faults. In this case, Current Imaging provides insight into the sample's behaviour yielding qualitatively comparable results to the more cumbersome cAFM technique. While the results of the TEM investigations including EDX mappings were inconclusive, the Current Imaging technique clearly shows that the root cause is located below the SiGe layer. By combining these techniques inside a FIB/SEM microscope, it is possible to locate and characterize a failure as well as prepare a TEM lamella for further investigation without the necessity to switch to a different tool.

Magnetic Current Imaging Revisited

Abstract Magnetic current imaging provides electrical fault isolation for shorts, leakage currents, resistive opens, and complete opens. In addition, it can be performed nondestructively from either side a die, wafer, packaged IC, or PCB. This article reviews the basic theory and attributes of MCI, describes the types of sensors used, and discusses general measurement procedures. It also presents application examples demonstrating recent advancements and improvements in MCI.

Magnetic Field Imaging for Non-Destructive 3D Package Fault Isolation

While microelectronic packages are becoming more and more advanced, the need for non-destructive Electrical Fault Isolation (EFI) becomes ever more critical for the entire product life-cycle ranging from the chip development yield enhancements to failures on product returns. In the beginning of product development, short failures are often the main issue while opens and cracks become the reliability problems after the product reaches the marketplace. In this paper we present Magnetic Field Imaging (MFI) as the one technique that can find all static defects: shorts, leakages and opens in a true non-destructive way.

Two-photon laser-assisted device alteration in silicon integrated-circuits

Optoelectronic imaging of integrated-circuits has revolutionized device design debug, failure analysis and electrical fault isolation; however modern probing techniques like laser-assisted device alteration (LADA) have failed to keep pace with the semiconductor industry's aggressive device scaling, meaning that previously satisfactory techniques no longer exhibit a sufficient ability to localize electrical faults, instead casting suspicion upon dozens of potential root-cause transistors. Here, we introduce a new high-resolution probing technique, two-photon laser-assisted device alteration (2pLADA), which exploits two-photon absorption (TPA) to provide precise three-dimensional localization of the photo-carriers injected by the TPA process, enabling us to implicate individual transistors separated by 100 nm. Furthermore, we illustrate the technique's capability to reveal speed-limiting transistor switching evolution with an unprecedented timing resolution approaching <10 ps. Together, the exceptional spatial and temporal resolutions demonstrated here now make it possible to extend optical fault localization to sub-14 nm technology nodes.

Effective Protection Technique for Electrical High-Impedance Fault Detection and Isolation

Electrical Medium voltage overhead distribution lines run for long distances to supply consumers, sometimes their live conductors fall on very high impedance surfaces limiting the short circuit current below the sensing level of the line protective relays. Fallen conductors, remains unknown for hours subjecting the humans and livestock to electrocution. Sad accidents have repeated in rural places in Saudi Arabia namely in Ain Dar, Dhobiaa, Baqaa, etc. Saudi Electricity company formed a committee to solve the problem, this committee studied the previous work done on this subject from the Saudi Electricity Company, Saudi Aramco, the Saudi Universities research work. Various technical meetings were conducted with the relays vendors to find a workable solution. The committee concluded that all the up to date substation protection relays are not facilitated with effective means of detecting all the concerned high impedance faults due to their dynamic and random nature. This author approached the problem by sensing the loss of conductor by voltage measuring relay at the terminal point. Operation of the voltage relay initiates a mechanical device to create a deliberate fault which can produce a sufficient current to be sensed by the upstream devices and isolate the faulty section in few seconds.

Scanning Auger of a specific via interface in an integrated circuit using a novel focused ion beam sample preparation technique

Auger depth profile analysis can be impeded by surface roughening during ion sputtering. This is especially noticeable when analyzing semiconductor devices because of the variety of materials that are susceptible to roughening, as well as the importance of very thin interfaces. A novel technique is presented in this article, which combines scanning Auger analysis with focused ion beam (FIB) thinning for analysis of single via interfacial structures in integrated circuit devices. After a failing structure was identified by electrical fault isolation techniques, FIB was used to remove all of the materials from the top of the device. The materials include polyimide, passivation, metal layers, and dielectric layers. The layers were removed to a level approximately 100Å above the via interface under a tungsten plug. A scanning Auger instrument was then used for Auger depth profiling of the single via. A thin oxidized interface was observed between Ti∕TiN glue layer and antireflection coating (ARC) TiN and was identified as the cause of the via failure. It would have been impossible for conventional sputter depth profiling to detect this thin oxidized layer buried under several layers of materials. Further investigation showed that the interfacial oxide is caused by backsputtering of ARC TiN during via etch and rf sputtering before Ti∕TiN glue deposition.

Electron Beam Induced Damage to Diffusion Resistors

Abstract Nanoprobing of transistors and resistors is increasing in importance for both design debug and electrical fault isolation. It is thus necessary to understand the impact of scanning a resistor or transistor with an electron beam in order to draw valid conclusions from nanoprobe measurements. In this article, the authors show that exposing samples to electron beams with energies above 4 keV can change the value of diffusion resistors by as much as 30% and that changes can occur at even lower voltages in areas of the sample covered with less material. The article also sheds light on why the changes occur.