Abstract
Buried via voids defect beneath the metal layer of an integrated circuit (IC) has always been a challenge to localize. The importance of dynamic electrical fault isolation (EFI) approaches, automated multi-level circuit net trace, and test bench simulation on buried via void localization are discussed in this paper. Three buried via void case studies will be discussed, including a hard functional failure, an ATPG soft failure, and a high dynamic leakage current (IDD) failure.
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