Electrical Fast Transient Test Research Articles

Conducted Coupling Model and Anti-Interference Filter Design for Digital Control Circuit Under Electrical Fast Transient Noise

Control and protection equipment working in complex electromagnetic environment often suffers from electrical fast transient (EFT) noise, which easily leads to the failure of digital control circuits of the equipment. In order to realize low-cost and effective anti-interference solutions to the failure problem, it is necessary to study the anti-interference quantitative design method of the digital control circuit. In this article, a conducted interference coupling model of the digital control circuit under EFT noise is established. As an important part of the coupling path, the impedance model of the chip is built. A black-box impedance modeling method of voltage regulator chip is proposed based on online measurement. The equivalent impedance model of the digital signal processing (DSP) chip is represented by the high-frequency model of the inductor. The coupling model is validated by comparing the measured results and simulated results of the terminal load port voltage. Then, a measurement and analysis method is presented to obtain the circuit failure threshold. By analyzing EFT test results at different frequencies and amplitudes, the influencing factor of the circuit failure is clarified, and the circuit failure threshold is obtained. Finally, based on the coupling model and the circuit failure threshold, a quantitative design method of an anti-interference filter is developed. The method is validated through filter prototyping for a 5 kHz/+2.0 kV EFT test.

A Research of Pulse Source for EFT Test of Electrical Vehicle Piles

A type of high-voltage pulse source technology generating double-exponential waveform pulse group was introduced. In this approach, the pulse interval could be adjusted with the step length of 100 μs, and the amplitude would reach up to 35 kV. This pulse source could be used to test the sensitivity of electric vehicle (EV) piles under electrical fast transient (EFT) interference. The theory of obtaining double-exponential wave and its generating circuit was analyzed, and then the influencing factors of the rising edge were expounded. A method of pulse insertion was adopted to generate a fast transient pulse group due to the limitation of the repeated operating frequency of switching devices. This method could be summarized as a common load fed by several parallel pulse sources, which were controlled and triggered in time sequence. Thus, a set of timing pulse could be obtained from the load ending. The feasibility of this method was also demonstrated. The electromagnetic interference cannot be avoidable because the load was fed by different timing sources. The high-voltage pulse generated initially causes the latter sources to be false-triggered with serious influence to the entire system. The interference generated by the couple circuit composed by distributed parameters, such as distributed capacitance and inductance, was also analyzed. A coupled model was established, analyzed, and simulated to prove the existence of the conducted interference and false triggering for other sources. The measure of conducted interference suppression was also presented. A set of experiments was carried out to show that different numbers of double-exponential pulse groups with different time intervals could be obtained.

Design and analyze of transient-induced latch-up in RS485 transceiver with on-chip TVS

The occurrence of transient induced latch up (TLU) in RS485 transceiver IC with on-chip Transient Voltage Suppressor (TVS) under electrical fast transient (EFT) test is studied. A RS485 transceiver fabricated by a 0.5-μm CDMOS process was used in the test, the latch-up and emission microscope (EMMI) tests are used for confirming the reason and position of latch-up. The trigger current injecting into the transceiver through RO port and generating the substrate current is the major cause of TLU under EFT test. Some measures in layout are taken to improve the TLU immunity of RS485 transceiver against EFT test.

SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance

A new silicon controlled rectifier (SCR)-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance is proposed. The circuit function to detect positive or negative electrical transients during system-level electrostatic discharge (ESD) and electrical fast transient (EFT) tests has been verified in silicon chip. The experimental results in a 0.18-μm CMOS process have confirmed that the new proposed detection circuit can successfully memorize the occurrence of system-level electrical transient disturbance events. The detection results can be cooperated with firmware design to execute system recovery procedures, therefore the immunity of microelectronic systems against system-level ESD or EFT tests can be effectively improved.

On-chip detection circuit for protection design in display panel against electrical fast transient (EFT) disturbance

A new on-chip detection circuit is proposed for electrical fast transient (EFT) protection design in a display system. For microelectronic products, electrical transient disturbances often cause upset or frozen states under the IEC test standard. The output signal of the proposed detection circuit can be used as a firmware index to execute system automatic recovery operations and to release the EFT-induced locked states in display panels. The circuit function to detect positive or negative electrical transients has been investigated in HSPICE simulation and verified in silicon chip. The experimental results have confirmed successful circuit performance under EFT tests. With hardware/firmware co-design, the immunity of a display system against electrical transient disturbance has been significantly improved.

New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance

A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18-μm complementary-metal-oxide-semiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.

Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test

The occurrence of transient-induced latchup (TLU) in CMOS integrated circuits (ICs) under electrical fast-transient (EFT) tests is studied. The test chip with the parasitic silicon-controlled-rectifier (SCR) structure fabricated by a 0.18-mum CMOS process was used in EFT tests. For physical mechanism characterization, the specific ldquoswept-backrdquo current caused by the minority carriers stored within the parasitic PNPN structure of CMOS ICs is the major cause of TLU under EFT tests. Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against TLU under EFT tests. By choosing the proper components in each noise filter network, the TLU immunity of CMOS ICs against EFT tests can be greatly improved.

The Effect of IEC-Like Fast Transients on <formula formulatype="inline"><tex Notation="TeX">$RC$</tex> </formula>-Triggered ESD Power Clamps

Four power-rail electrostatic-discharge (ESD) clamp circuits with different ESD-transient detection circuits have been fabricated in a 0.18-mum CMOS process to investigate their susceptibility against electrical fast-transient (EFT) tests. Under EFT tests, where the integrated circuits in a microelectronic system have been powered up, the feedback loop used in the power-rail ESD clamp circuits may lock the ESD-clamping NMOS in a ldquolatch-onrdquo state. Such a latch-on ESD-clamping NMOS will conduct a huge current between the power lines to perform a latchuplike failure after EFT tests. A modified power-rail ESD clamp circuit has been proposed to solve this latchuplike failure and to provide a high-enough chip-level ESD robustness.

Electrical fast-transient test: conducted and radiated disturbance determination by a complete source modeling

Tests against electrical fast transient/burst (EFT) represent a serious threat for modern high-speed electronics: besides the conducted injection of high amplitude pulse, a strong radiated field is produced during this test. The prediction of the effects of this test during the equipment early design stage requires the equivalent circuit of the generator: the output waveform into a resistive 50-/spl Omega/ load is not sufficient to recover the complete circuit, including inductive component and parasitic elements. These are essential to predict the disturbance produced in arbitrary loads, as the equipment under test can be viewed. This paper describes how to characterize the EFT generator by means of the measurement of the output voltage and current produced in presence of known loads; moreover, a procedure to calculate the current on the equipment power cord is shown, based on the use of a circuit simulator (PSPICE). Finally, the disturbance produced on different loads and the radiated field during the test are calculated and experimentally validated.

Investigation of radiated susceptibility during EFT tests

The aim of this paper is to focus on a problem: during an electrical fast transient (EFT) conducted susceptibility test, a very strong radiated field is produced and a radiated coupling with the internal circuitry of the equipment under test (EUT) occurs. Therefore in case of EUT malfunctions, it is difficult to understand whether the resulting failures are due to the injected conducted current (requiring a filtering action) or to the impinging radiated EM field (requiring a shielding action). A model to describe the EM radiation, coming from the current flowing along the EUT power cord, is presented as well as its experimental validation.

Electrical fast-transient tests: applications and limitations

According to a recent standard of the International Electrical Commission (IEC Publication 801-4, 1988), a fast-transient test must be applied to the connecting cables of electronic equipment to demonstrate equipment immunity to fast transients resulting from switching. Tests and simulations of the propagation and attenuation of these fast transients in typical connecting cables are described, placing the IEC requirements in perspective.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>