Electrical Characteristics Research Articles

Influence of High-κ Dielectrics Integration on ALD-Based MoS2 Field-Effect Transistor Performance.

The integration of high-κ dielectrics on MoS2 field-effect transistors (FETs) is essential for the realization of MoS2 in ultrascaled nanoelectronic devices and circuits. Most studies covering this topic are based on exfoliated MoS2 flakes or chemical vapor deposition (CVD) grown MoS2 films, whereas other techniques, such as atomic layer deposition (ALD), are also gaining attention for the growth of MoS2 in recent years. In this work, we grow large-area MoS2 by means of plasma-enhanced (PE-)ALD and evaluate the influence of high-κ dielectrics on the properties of ALD-based MoS2 FETs through electrical characterization combined with surface-chemical and high-resolution scanning transmission electron microscopy (HR-STEM) analyses. We grow HfO x , AlO x , or both by means of PE-ALD or thermal ALD on our fabricated devices and show that, in addition to the dielectric constant, three other major parameters related to the processing of the dielectrics can simultaneously affect the MoS2 FET electrical characteristics and govern its doping. These parameters are the stoichiometry of the dielectric, its carbon impurity content, and the degree to which the MoS2 surface oxidizes upon the dielectric growth. When grown at 100 °C, our HfO x films are oxygen-vacant whereas our AlO x films are oxygen-rich. In addition, carbon impurities are incorporated into the dielectrics at low deposition temperatures, being one of the likely causes of the MoS2 FET overall n-type performance in all of the studied cases. Our investigations also reveal that PE-ALD of HfO x or AlO x oxidizes the MoS2 surface, whereas thermal ALD AlO x leaves MoS2 almost intact. In this respect, if thermal ALD AlO x of proper thickness is grown between MoS2 and HfO x , it can reduce the degree to which the MoS2 surface oxidizes by HfO x and meanwhile improve the total dielectric constant, altogether leading to the most optimal electrical performance in ALD-based MoS2 FETs.

Effects of ALD Deposition Cycles of Al2O3 on the Morphology and Performance of FTO-Based Dye-Sensitized Solar Cells

In dye-sensitized solar cells (DSSCs), materials classified as Transparent Conducting Oxides (TCOs) have the capacity to conduct electricity and transmit light at the same time. Their exceptional blend of optical transparency and electrical conductivity makes them popular choices for transparent electrodes in DSSCs. Fluorine Tin Oxide (FTO) was utilized in this experiment. The optical and electrical characteristics of TCOs may be negatively impacted by their frequent exposure to hostile environments and potential for deterioration. TCOs are coated with passivating layers to increase their performance, stability, and defense against environmental elements including oxygen, moisture, and chemical pollutants. Because of its superior dielectric qualities, strong chemical stability, and suitability with TCO materials, aluminum oxide (Al2O3) was utilized as a passivating layer for the FTO. In this research work, Al2O3 was deposited via atomic layer deposition (ALD) to form thin mesoporous layers as a passivator in the photoanode (working electrode). The work focuses on finding an appropriate thickness of Al2O3 for optimum performance of the dye-sensitized solar cells. The solar simulation and sheet resistance analysis clearly showed 200 cycles of Al2O3 to exhibit an efficiency of 4.31%, which was the most efficient performance. The surface morphology and topography of all samples were discussed and analyzed.

(Invited) Influence of the Semiconductor Thin Film Morphologies on Dntt Organic Electronic Devices Performances

Interest in organic semiconductors has grown enormously in the last few years, indeed their use in microelectronics is continuously rising up in a large range of fields, spanning from academic to industrial new applications [1]. They provide a large number of interesting properties that have pushed a gradual replacement of classical amorphous silicon-based devices with organic ones [2], as they promise to be the best candidates as drivers of the necessary green and digital transition and become the building blocks in a huge number of future applications.In most devices, particularly in OTFTs, the quality and properties of the interface between semiconductor and dielectric are of fundamental importance for the device electrical characteristics [3-4]. Dinaphtho [2,3-b:2′,3′-f] thieno [3,2-b] thiophene (DNTT)-based OTFTs are among the best-known devices as they provide good performances in terms of charge mobility, good stability as well as easy processing and they are particularly suitable to study deeper the role of insulator/semiconductor interface [5-6]. It has been widely reported that the best performances of the small molecule organic based transistors, in terms of charge mobility as well as stability, are obtained when the molecules align with their long axis almost perpendicular to the growth surface. The DNTT molecules deposited on SiO2, align to form a homogeneous film, which results to be highly crystalline and provides good transport properties. However, in DNTT-based OTFTs different insulator surfaces, above which the active layer is grown, can provide different properties in terms of morphology and surface energy so that the electrical performances of the resulted devices can span in a wide range [7].In this work, we have studied the growth of DNTT semiconductor thin films on two different dielectric materials relating the ordered DNTT thin film structure to the OTFTs' electrical characteristics. OTFTs have been fabricated with Bottom Gate Top Contact (BGTC) configuration using thermal SiO2 or a double layer of SiO2/CytopTM as gate dielectrics. Semiconductor thin films, with thicknesses ranging from 3 nm to 50 nm, were detailed analyzed with high resolution AFM and XRD measurements (Fig. 1a, b, c, d) for different growth conditions to understand the morphologies of the films starting by the very first ordered layers of DNTT semiconductors. Our measurements show that DNTT molecules on SiO2 and Cytop pack into ordered structures placing themselves with their long axis perpendicular to the plane of the substrate (edge-on). However, in the case of DNTT on SiO2, a portion of ordered molecules can lie horizontally on the substrate (face-on). This causes an increase of defective states for the majority carriers in the conductive channel of the transistor, with a consequent reduction of the field-effect mobility (Fig. 1a, b). Numerical simulations were performed to analyze the effects of different semiconductor film morphologies on the electrical characteristics of the OTFTs. We also show that the morphological semiconductor differences lead to better performances for organic phototransistors based on DNTT/Cytop interface [8].[1] C. Wang et al., Chemical reviews 2012, 112 (4), 2208-2267.[2] Y. Bonnassieux et al., Flexible and Printed Electronics 2021, 6 (2), 023001.[3] H. I. Un et al., Advanced Science 2019, 6 (20), 1900375.[4] H. Sirringhaus et al., Advanced materials 2014, 26 (9), 1319-1335.[5] H. Chang et al., Org. Electron., 2015, 22, 86-91.[6] Q. Wang et al., ACS applied materials & interfaces 2018, 10 (26), 22513-22519.[7] M. Geiger et al., Advanced Materials Interfaces 2020, 7 (10), 1902145.[8] S. Calvi, et al., Org. Electron., 2022, 102, 106452. Figure 1

( General Student Poster Award Winner, 1st Place) Organic Electrochemical Transistors for High-Performance Electrocorticography Recording

Instrumentation used in biopotential recordings is paramount in ensuring correct representation of electrophysiological activity, affecting medical diagnosis and intervention. Additionally, high signal fidelity challenges the engineering of future neural interfaces, requiring high Signal to Noise Ratios (SNR), high spatial and temporal resolution, and low-cost. Recently, transistor-based technologies have garnered increased attention and are being used as bio-electronic interfaces due to their inherent amplification capabilities. Specifically, Organic Electrochemical Transistors (OECTs) stand at the forefront of this technological shift given their low voltage operation, miniature size, biocompatibility, and high transconductance (gm), a measure of amplification. Within an electrolyte environment, OECT channel conductivity is modulated by the charge carrier concentration, changing with the voltage level inside the medium, which, if tied to a biopotential, can be concluded by measuring the drain current.In this work, we designed and developed an OECT-based neural interface employing an in-plane gate, pioneering its use in-vivo to guarantee operation at peak gm. For device fabrication, we employed inkjet printing, thus avoiding cumbersome multi-step cleanroom microfabrication, reducing costs and facilitating production.OECTs were fabricated following a three-step fabrication process. First, gold nanoparticle ink was used to pattern the source, drain, and gate on a polyimide backbone. Next, polyimide ink was deposited over the connecting leads for insulation, and finally, poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) was layered to form the semiconducting channel. The devices’ electrical characteristics were assessed in a phosphate buffer solution (PBS) with either the gold in-plane electrode or an Ag/AgCl probe as the gate. To achieve efficient in-plane gating, the gold electrode was modified with PEDOT:PSS layering to decrease the voltage drop across the gate/electrolyte interface and minimize spatial footprint. To showcase the use and effectiveness of including an in-plane gate, artificial hippocampal neuronal spikes were fed to the OECT at different gate biases. The in-vivo performance of the OECT was evaluated by implanting it onto the cortex of a rat model and assessing its efficacy in recording electrocorticographic (ECoG) activity. Furthermore, low impedance PEDOT:PSS-coated gold passive electrodes were fabricated adjacent to the transistor’s channel for performance comparison. Seizures were induced via intra-amygdala injection of kainic acid (KA), and recordings were acquired from the sensory-motor cortex.Inkjet-printed OECTs realized in this work had a channel length of 15µm, a width of 130µm and a channel thickness of 250nm. To efficiently gate the device, the voltage drop across the gate/electrolyte interface must be negligible compared to the one experienced at the channel. This can be achieved by increasing the channel-relative gate capacitance, and we show that PEDOT:PSS coating of the electrode efficiently minimizes the drop compared to increasing its size, which is favorable in a spatially limited application like ECoG recordings. In addition, the developed OECTs achieved a high gm of 14mS, a quick response time of 0.5ms, and a compact channel area of 1950µm2, setting our OECT apart from existing high performing devices in literature. In addition, we highlight the importance of adequate material selection for source and drain metals and channel thickness in controlling the operational bandwidth of the device, given that high frequency oscillations, which are typically seen in seizure activity, present a challenge to OECTs that experiencing intrinsic gm drops at high frequencies. Upon comparison of gold and silver nanoparticle inks, results show that the usage of gold increases cut-off frequency for both thick and thin channels. Furthermore, we demonstrate that applying a cathodic potential through an in-plane gate placed in proximity to the channel ensures operation at peak transconductance where amplification is at its highest. At optimal operation, OECT peak amplitudes increased by up to 133% compared to the absence of the gate, accompanied by an increase in SNR. In vivo, OECTs outperform low-impedance passive electrodes and successfully record distinct seizure features, mainly sharp spike-wave discharges, and bursts, achieving a high SNR of 48dB.Next generation neural interfaces must provide high fidelity and localized recordings. Electrochemical solutions arise as a promising candidate to replace conventional passive electrodes, offering high resolution and SNR. In this work, we designed and built low-cost OECTs using inkjet printing, coupled with an in-plane gate to maximize performance. The developed sensor is employed in vivo and shown to outperform low-impedance passive electrodes by recording distinct seizure phases. This technology shows great promise to develop into a general-purpose active recording component in the diagnosis and monitoring of neurological disorders or other applications in biopotential sensing.

Exploring the Relationship between Mechanical Properties and Electrical Impedance in Cement-Based Composites Incorporating Gold Nanoparticles.

Structural health monitoring applications have gained significant attention in recent research, particularly in the study of the mechanical-electrical properties of materials such as cement-based composites. While most researchers have focused on the piezoresistive properties of cement-based composites under compressive stress, exploring the electrical impedance of such materials can provide valuable insights into the relationship between their mechanical and electrical characteristics. In this study, we investigated the connection between the mechanical properties and electrical impedance of cement-based composites modified with Au nanoparticles. Cylindrical samples with dimensions of 3 cm in diameter and 6 cm in length were prepared with a ratio of w/c = 0.47. The Au nanoparticles (Au NPs) were synthesized using pulsed laser ablation in liquids, and their size distribution was analyzed through dynamical light scattering. Mechanical properties were evaluated by analyzing the Young modulus derived from strain-stress curves obtained at various force rates. Electrical properties were measured by means of electrical impedance spectroscopy. The experimental results revealed a notable reduction of 91% in the mechanical properties of Au NPs-cement compounds, while their electrical properties demonstrated a significant improvement of 65%. Interestingly, the decrease in mechanical properties resulting from the inclusion of gold nanoparticles in cementitious materials was found to be comparable to that resulting from variations in the water/cement ratios or the hydration reaction.

(Invited) A Neural Compact Model Based on Transfer Learning for Organic FETs

Organic field-effect transistors (organic FETs) exhibit highly non-linear electrical characteristics due to their distinctive transport mechanism manifested by thermally-assisted hopping via localized states randomly distributed in both energy and space domains. This feature impedes the establishment of an analytical compact model. In this context, we present an approach to adopt artificial neural networks (ANN) for the development of a compact model, namely a neural compact model, by exploiting the powerful ability of the ANN to describe a non-linear function accurately. In addition, we evaluate the knowledge transfer method to reduce learning time and improve accuracy even when the data is scarce and costly. By technology computer-aided design simulation, we constructed a dataset of electrical characteristics of organic FETs with Gaussian disorder which is calibrated to the experimental measurement. Subsequently, we constructed and compared neural compact models based on conventional deep learning and transfer learning. We showed that the neural compact model with transfer learning provides an equivalent accuracy at a shorter modeling time. A complex dependence on the gate voltage, drain voltage, and temperature is successfully modeled over a wide range of operation regimes and temperatures.

(Invited) Consideration on Gate Stack Formation Processes of Ultrawide Bandgap Ga2O3 with SiO2 Dielectric Layer

MOSFETs on β-Ga2O3 are expected to be a high-efficient and cost-effective alternative option of high-voltage power devices. Taking account of the reliability and the large conduction-band offset against β-Ga2O3, it would be reasonable to employ SiO2 as the gate dieletric. In this study we investigated the effects of post-deposition annealing (PDA) on SiO2/β-Ga2O3 MOS gate stacks, in terms of the MOS electrical characteristics and the band alignment.β-Ga2O3 (001) wafers with ~2×1016 cm-3 n-type doped epitaxial layers were cleaned in diluted HF solution, and SiO2 films were deposited by electron-beam (EB) evaporation of Si in O2 ambient of ~1×10-2 Pa, followed by PDA at various temperatures from 600 to 1000℃ in either O2 or N2 ambient. Au was evaporated as gate electrode to form MOS capacitors. X-ray photoelectron spectroscopy (XPS) was conducted on the stacks with ~3nm-thick SiO2 for the evaluation of band alignment. Ultraviolet photoelectron spectroscopy (UPS) was also employed to determine the band diagram of β-Ga2O3 (001).Nearly-ideal capacitance-voltage characteristics were obtained for the MOS capacitor fabricated with O2-PDA at 1000℃. The interface state density (Dit) determined by conductance method decreased down to ~1010 cm-3 at the energy level of EC−0.2 eV by PDA at higher temperature. The hysteresis width (ΔVhys) of C-V curves was smaller for the samples annealed at higher temperatures. The flatband voltage (VFB) shift after O2-PDA resulted in VFB close to the ideal value estimated from the physical properties of Au and Ga2O3, suggesting that fixed charge density at the interface would be minimized. However, PDA in N2 at 1000℃ resulted in a negative shift of VFB, which indicates the formation of positive fixed charges in the stack. The beneficial influences of O2-PDA on those characteristics suggest that an oxygen deficiency introduced near the interface is one of the origins of interface defect states. It is noteworthy that Ga3d XPS on the surface of Ga2O3 substrate always shows a tailing in lower binding energy side, which is indicating oxygen deficiency on the surface. The intensity of this lower-binding-energy component reduced significantly when a bare-Ga2O3 substate was annealed in O2, however, it did not decrease efficiently even after O2-PDA when the surface was covered with SiO2. This is probably due to the oxygen rearrangement at SiO2/Ga2O3 interface determined by the difference of material properties of those oxides. This fact suggests that the Ga2O3 surface easily forms oxygen vacancies when it is covered with SiO2. This would be the reason why the formation of interface defect states is not suppressed without O2-PDA.Next the band diagram of β-Ga2O3 (001) substrate was investigated by UPS analysis where the energy level of valence band edge referring to the vacuum level was evaluted from the energy difference between minimum (cut-off) and maximum edges of the obtained kinetic energy spectra of photoelectrons. As a result we found the valence band edge of of β-Ga2O3 (001) was ~8.2 eV below the vacuum level, where the influences of O2 annealing at 1000℃ on the valence band edge energy level was limited to the shift within ~0.1eV. This would tell us the valence band offset between SiO2 and Ga2O3 should be around ~1.1eV, and the conduction band offset between them is to be around 2.8-2.9eV, by taking account of the well-reported SiO2 band diagram and assuming the bandgap of β-Ga2O3 as 4.7eV. On the other hand, the valence band offset estimated from the deconvolution of the XPS valence band spectrum for a ~3nm-thick SiO2/β-Ga2O3 stack from the energy edge difference between the deconvoluted spectra corresponding to SiO2 and Ga2O3, was a few hundreds of mV smaller than the above expected value (~1.1eV). This discrepancy is indicating the formation of an interface dipole layer between SiO2 and Ga2O3 with a pair of nagative and positive charges aligned at the interface to cause a shift in the band alignment. The magnitude of such dipole was indicated to be more significant (~0.5eV) for the stack after PDA at 1000℃, whereas it was less (0.2~0.3eV) after PDA at 600℃.In conclusion, we demonstrated that SiO2/β-Ga2O3 (001) MOS capacitors showed nearly-ideal electrical characteristics with significantly reduced interface defect density and small fixed charge density by applying O2-PDA. The band alignment of SiO2/β-Ga2O3 (001) MOS stack was clarified by photoelectron spectroscopy to confirm a very large conduction band offset of the stack, but an influence of the formation of interface dipole layer between SiO2 and Ga2O3 on the band alighment was also indicated.

Fabrication of Nano-Carbon-Based Sustainable Perovskite Solar Cells

The rising need for sustainable energy solutions has fuelled considerable research into novel technologies that harness solar energy for efficient and scalable energy storage. Carbon nanotubes (CNTs) have emerged as feasible candidates for these applications due to their unique properties, such as high surface area, better electrical conductivity, and chemical stability.This report focuses on the design and fabrication of cost-effective nano-carbon-based perovskite solar cells (PSCs) and discusses their potential for clean energy generation and storage. This experimental study shows a novel technique to increase the sustainability the conventional fluorine-doped tin oxide (FTO) substrate with an Indium Tin Oxide (ITO) derived from electronic waste and incorporating nanocarbon based-graphene with solution-based techniques. This addition serves as a good basis for the ITO coating, aids charge transport in the perovskite solar cell, and promotes uniform covering maximum electrical conductivity, and transparency. Being the transparent conducting electrode, the CNTs is infused with the upcycled ITO coated glass and was included in the perovskite solar cell architecture, which replaces the traditional ITO electrode, lowering material costs, and improving the circular economy for energy storage devices, and a cleaner energy future.The ITO extraction process entails recovering indium and tin from mobile phones using an environmentally friendly and economical chemical etching process using hydrochloric acid (HCl) to remove the ITO layer. To ensure the purity and structural integrity of the ITO nanoparticles, they were rigorously characterized using X-ray diffraction, scanning electron microscopy, and energy-dispersive X-ray spectroscopy. After depositing a perovskite- CNTs precursor solution on the ITO layer glass substrate, the light-absorbing layer was annealed. Electron transport and hole-blocking layers were then deposited utilizing solution processing techniques using the PEDOT: PSS and metal electrodes were deposited to complete the device manufacturing. The current-voltage (J-V) relationship was used to compute the open-circuit voltage, short-circuit current density, fill factor (FF), and power conversion efficiency (PCE) of a solar cell. Electrical characterization allow for the calculation of solar cell performance metrics such as short-circuit current (Isc), short-circuit current density (Jsc), and open-circuit voltage (Voc). These findings imply that employing e-waste-derived ITO on graphene substrates to create high-efficiency perovskite solar cells is a realistic option. This research provides a sustainable and cost-effective method for producing high-performance perovskite solar cells by eco-friendly upcycling e-waste for ITO extraction, addressing the critical issue of e-trash management. Keywords Perovskite solar cells, CNTs, sustainable energy, energy conversion.

(Invited) Non-Fullerene Acceptor in Organic Solar Cells Toward Improving Performance as Indoor Light Energy Harvester

Research in organic solar cells aims to develop new materials that improve efficiency. The inception of emerging non-fullerene acceptors (NFAs) by replacing the fullerene counterpart in organic solar cells (OSCs) has pushed the bulk-heterojunction based photovoltaics to achieve efficiencies around 18% [1-6]. In order to produce efficient OSCs, it is required to have donor and acceptor materials with matching absorption bands in the Vis-NIR range, high charge-carrier mobility, and a small energy offset to minimize voltage losses. Mainly, the development of Y7 NFA molecule has improved power conversion efficiencies by pairing selected polymer donors, such as PM6 [7, 8]. Nowadays, OSCs have attracted great attention for being used as indoor light energy harvesters. The organic materials in the active layer can have tuned optical band gaps, providing an absorption spectrum that matches with emission spectra of several indoor lights, e.g., halogen lights, LED (light-emitting diodes), and FLs (fluorescent lamp), which have different emitting spectra [9, 10].The use of OSCs for indoor light harvesting applications is promising for integration into low-power indoor electronic devices from microwatts to milliwatts, such as data transfer systems, alarm systems and distributed controls. Moreover, the OSCs have the possibility to be used with power wireless sensor nodes connected to the Internet of Things. At present, LEDs are the most popular low-light level sources which can be found in offices and homes. The intensity of the light emitted by an artificial light source, per unit area of a surface is called illuminance and measured in units of lux (lx). A level 500 lx is typically recommended for office environments and 200 lx for living room environments.In this research, we have been aiming at the performance and stability over time of organic solar cells under LED illumination using fullerene and non-fullerene acceptors. We have chosen as the indoor illumination source an LED lamp with a color temperature of 3000 K and color rendering index (CRI) > 80 following the protocols ISOS [11]. The LED lamp output illuminances were varied in the range from 200 to 1500 lx. We have used PM6 as polymer donor material due to their absorption spectrum and energy band gaps well-matched to the incident LED spectrum. In order to research the improvement of the performance of OSCs under indoor illumination we have compared PC70BM fullerene acceptor with ITIC-M, Y6-O, and Y7 non-fullerene acceptors. As a result, under 1000 lx illumination we achieved PCEs from ~ 12% using Y6-O, ~ 15% using PC70BM, ~16% using Y7 up to more than 18% efficiency using ITIC-M. The study is performed including optical and electrical characterization with the purpose of understanding the behavior and the transport processes taking place in the device. In future work, we focus on the stability of the encapsulated OSCs under continuous LED illumination following the agreed stability testing protocols to study which active layer turns out to be more stable under these conditions. Acknowledgements: This work was supported by the Ministerio de Ciencia, Innovación y Universidades (MICINN/FEDER) PDI2021-128342OB-I00, by the Agency for Management of University and Research Grants (AGAUR) ref. 2021-SGR-00739, and by the Catalan Institution for Research and Advanced Studies (ICREA) under the ICREA Academia Award. M. Ramírez-Como acknowledge to CONAHCYT ref. BPPA-20220624083033039-2364083.

(Invited) Deformable Electronics Based on Strain-Engineered Van Der Waals Materials

Materials exhibit drastically different physical and chemical properties as their dimensionality varies. Atomically-thin van der Waals (vdW) materials possess unique mechanical, electrical, optical, and thermal characteristics, originated from quantum confined low-dimensionality and a lack of dangling bond. In particular, strong in-plane covalent bonding and weak interlayer vdW interaction of two-dimensional (2D) vdW materials enable exceptional combination of mechanical properties, such as high Young’s modulus, high in-plane strength, and ultralow bending stiffness at a level of cell membrane. Moreover, mechanical strain can induce modulation of electronic and phononic band structures of 2D vdW materials more effectively due to mechanical resilience and high surface-to-volume ratio. For these reasons, deformation engineering has garnered substantial interest in mechanics, materials and electronics communities as a new tuning knob for emerging phenomena and functionalities of 2D vdW materials. In this talk, I will discuss deformation engineering of 2D vdW materials – (1) active and dynamic deformation strategies, including in-plane interfacial slippage and out-of-plane structural deformation, (2) deformation strain induced phenomena, and (3) emerging device concepts based on deformation engineering of 2D vdW materials.

Low Frequency Electronic Noise Characterization of Au-W/β-Ga2O3 Schottky Diodes

Ultra-wide bandgap (UWBG) semiconductors have attracted tremendous amount of interest for applications in high-power electronics and solar-blind UV photodetectors. In particular, β-Ga2O3 has attracted significant research attention in recent years due to its promising electrical and optical characteristics including a large bandgap, high breakdown electrical field, and large Baliga’s figure of merit compared to well-established wide-bandgap technologies such as GaN and SiC [1].Low frequency electronic noise, which is present in all electronic devices, can be used as a diagnostic tool for semiconductor material and device characterization. By studying the low frequency noise in semiconductor materials and devices, the physics associated with the noise properties of bulk and interface defects and traps can be investigated [2]. Measurement of low frequency noise is also crucial for evaluating material quality and device reliability.In this work, we investigate the forward-bias diode parameters and low-frequency electronic noise in Au-W/β-Ga2O3 Schottky barrier diodes. The Schottky contact is formed by depositing 20 nm of Tungsten (W) using dc sputtering followed by 340 nm of Gold (Au) using e-beam evaporation, and subsequent annealing [3].We first measure the I-V characteristics and extract important diode parameters, such as the Schottky barrier height, ideality factor, and series resistance from room temperature forward-bias current-voltage characteristics. The extracted Schottky barrier height for these devices is in the range 0.7-0.8 eV and the ideality factor is approximately 1.2.We next measure the low-frequency electronic noise in Au-W/β-Ga2O3 Schottky diodes at different forward bias voltages at room temperature. We find that the current noise spectral density exhibits 1/f-type behavior for all forward bias voltages at low frequency with an exponent ranging from 0.75 to 1.15, indicating that the low frequency noise of these devices is dominated by excess (flicker) noise. No Lorentzian-shaped generation-recombination (G-R) noise is observed. At low frequencies, the shot noise contribution is found to be negligible for the values of the current in our devices, and the total noise is 1/f-limited.We also investigate the dependence of the current noise spectral density on forward bias current, revealing different relationships in different current regimes. At low currents, the noise spectral density is found to scale approximately as the square of current, whereas at high currents, the noise spectral density begins to saturate. Such noise behavior can be attributed to different noise sources dominating in different current regimes. Furthermore, using the noise figure of merit adapted for ultra-wide bandgap semiconductor devices [4], we find that the Au-W/β-Ga2O3 devices have lower noise levels compared to other emerging UWBG materials and similar noise levels as well-established technologies such as GaN.These results provide important insights into the electronic noise properties of Au-W/β-Ga2O3 Schottky diodes and show that low frequency noise characterization is an important diagnostic tool for assessing the quality and reliability of gallium oxide based wide-bandgap materials and device technologies.

New Charged Interfaces for Energy Conversion and Catalysis

Charged interfaces are key areas for charge transfer and chemical reactions. Studying these interfaces at the microscopic level, especially in constructing and characterizing specific structures, understanding charge transfer, and managing chemical reactions, is crucial but challenging. Our work focuses on three innovative interface structures: solid/solid triboelectric, liquid/gas electrified, and solid/ultrathin heterojunction interfaces. We have achieved significant insights into the charge transfer mechanisms within these electrified systems and effectively controlled catalytic reactions at these interfaces.Key findings include: Development of new concepts for contact electrification and electrostatic-induced coupling at solid/solid interfaces, leading to novel applications in energy conversion and catalysis. We introduced the concept of mechanical-electric-catalytic reactions based on triboelectric interfaces and achieved direct synthesis of hydrogen peroxide through friction-catalysis under normal conditions.Effective control of reaction kinetics and selectivity in charged microdroplet liquid/gas electrified interfaces by adjusting parameters like droplet evaporation rates and electric field characteristics. This approach led to efficient production of hydrogen peroxide and selective conversion of carbon dioxide.Precise atomic-level construction and sub-nanometer characterization of solid/ultrathin heterojunction interfaces, exemplified by gold/graphene interfaces. This included the development of a gold/ultrathin palladium/single-layer ruthenium structure, enabling in-depth study of hydroxylation reactions and the influence of palladium interlayers on ruthenium's catalytic efficiency.

Electrical and Optical Characterization of Atmospheric Pressure Plasmas for the Treatment of OPV Materials

In the last years, non-equilibrium cold plasma at atmospheric pressure have led to numerous opportunities for material treatment. Depending on the gas mixtures, the electrodes configurations, the electrical waveform used to generate the discharge, or the material, a wide range of surface properties can be created. Among the plethora of applications, the organic photovoltaic (OPV) community has recently explored the use of plasma [1]. Thanks to the versatility of the cold atmospheric pressure plasmas (CAPP), all the layers used in the OPV cells could be potentially treated and modified. The use of dry atmospheric pressure processes also opens the doors to fast treatments at reduced cost compared to low pressure [2].Possible CAPP configurations for the OPV include plasma jets and dielectric barrier discharges (DBD) in volume or surface [3]. Among the different use of plasma in OPV, surface cleaning has been largely studied. For example, the removal of organic contaminants from indium tin oxide (ITO) layer have successfully been achieved with all the aforementioned configurations as well as different gas mixtures such as N2, O2, or He [4–6]. Other interesting mechanisms, such as the passivation of the electron transport layer [7], the modification of the work function [8], or for the encapsulation of the whole OPV cells [9] have been also explored.Still, whatever the material, either the metallic electrodes, the semiconductive active layer, or the dielectric substrates, a fine control of the plasma properties is necessary to ensure the good reproducibility and the stability of the process. It is hence necessary to characterize the physical regime and clarify the chemical reactions suitable to assess the good operation of the process during the material treatment.This work focuses on the use of electrical measurements and optical emission spectroscopy (OES) to retrieve key parameters from the process, like the discharge regime (Townsend vs filamentary), the capacitances of the system, or the power dissipated during the treatment [10]. In this context, this work aims at characterizing different discharge regimes for the surface treatment of thin characteristic layers employed in OPV (i.e., ITO, fluorine doped tin oxide (FTO) and zinc oxide). The influence of different electrical signals (low frequency sinusoidal voltage vs nanopulse), as well as different configurations and dielectric materials are compared. In order to link and allow to use such measurement as monitoring tools for the treatment process of materials used in OPV cells, the treated surfaces are also analyzed by SEM and contact angle. The extracted quantities from the plasma diagnostics could hence be used as a predictive tool to forecast the final properties of the treated materials and improve the processes of material treatment in OPV.[1] Mariotti et al. https://doi.org/10.1002/ppap.201500187[2] Vida et al. https://doi.org/10.37904/nanocon.2019.8646[3] Homola et al. https://doi.org/10.1016/B978-0-323-89930-7.00001-7[4] Chiang et al. https://doi.org/10.1007/s11090-010-9237-4[5] Yi et al. https://doi.org/10.1016/j.surfcoat.2003.08.011[6] Hvojnik et al. https://doi.org/10.1016/j.mssp.2021.105850[7] Polydorou et al. https://doi.org/10.1039/C6TA03594A[8] Chaney et al. https://doi.org/10.1016/S0169-4332(01)00347-6[9] Juillard et al. https://doi.org/10.1002/admi.202000293[10] Pipa et al. https://doi.org/10.3390/atoms7010014

(Invited) Understanding Carrier-Selective Catalyst/Semiconductor Contacts in Water-Splitting Photoelectrodes and Photocatalyst Particles

Heterogeneous electrochemical processes, including photoelectrochemical water splitting to evolve hydrogen and oxygen using electrocatalyst-coated semiconductors, are driven by the accumulation of charge carriers and thus the interfacial electrochemical potential gradients that promote charge transfer. Conventional electrochemical techniques measure/control potentials at the conductive substrate or semiconductor ohmic contact, but are unable to isolate processes and electrochemical potentials at the surface during operation. I will discuss how the nanoelectrode tip of an atomic-force-microscope cantilever can effectively sense the surface electrochemical potential of electrocatalysts coating semiconductor photoelectrodes during operation. This data can be combined with ex-situ electrical measurements, spectroscopy, and materials characterization approaches to provide a comprehensive physical picture of how excited electrons and holes can be effectively separated and catalyst/semiconductor contacts. This new understanding is particularly important for the design of photocatalyst particles where direct electrical measurements of catalyst/semiconductor interface properties is not possible. In these systems we are applying spectroscopic techniques, for example ambient pressure x-ray photoelectron spectroscopy and Stark-effect spectroscopy to understand electric and electrochemical potential distribution and how nanoscale, adaptive, heterogeneous contacts can be controlled to design higher performance photochemical systems.

Impact of Oxide Charges on The Minority Carrier Response in MOS(p) Devices With Al2O3/SiO2 Gate Stacks under Strong Inversion Condition

Admittance measurement, including capacitance and conductance, is very useful to analyze the electrical characteristics of metal-oxide-semiconductor (MOS) systems. These techniques offer insights into various device properties, including interface trap density and minority carrier lifetime in the substrate. It is essential to note that, apart from the gate area, the oxide region beyond the device could significantly influence measurement results [1]-[2]. In this work, a compact model proposed in [3] was used to clarify an unusual minority carrier response time observed in experimental data. The results proved the heightened sensitivity of device alternating current (AC) characteristics to oxide charges in the outer region. Additionally, the dependencies of oxide thickness and quality on the transition frequency (ωm) of devices were explored.The MOS (Al/AlOx/SiO2/p-Si) structure illustrated in Fig. 1 was employed in this study. Aluminum oxide region is under the gate electrode, while silicon oxide (SiO2) covers the entire wafer. Table 1 summarizes samples (S1 to S5) with consistent aluminum oxide thickness but diverse SiO2 thickness. Fig 2. shows the process flow and the anodic oxidation (ANO) system. By tilting the wafer at a specific angle during ANO, a high-quality SiO2 layer with different thicknesses on a single wafer could be obtained. Fig 3(a) to (d) illustrate the capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics of devices with varying SiO2 thicknesses. All devices exhibit low-frequency capacitance characteristics in strong inversion regions with thickness-dependent minority carrier response, particularly at 10kHz. Additionally, devices show different thicknesses depending on G-V characteristics at 1MHz and 10kHz. Fig 4(a) and (b) illustrate the Cinv/Cox ratio for varied oxide thicknesses and Gm/ω characteristics under strong inversion bias (VG = +3V). Gm means the measurement conductance. Following established research [3], peak Gm/ω magnitudes would occur at ωm. Table 2 reveals microsecond-range response times (τR) at ωm, considerably faster than conventional silicon minority carrier lifetimes (usually 1 ms to 100 ms). Moreover, decreasing oxide thickness shifts the ωm toward lower values.To explain this observed phenomenon, the environment outside the devices should be taken into consideration. Fig 5(a) and (b) show the schematic diagram and AC signal model proposed in [1] and [2]. Oxide charges in the outer region would deplete majority carriers and invert the p-type silicon surface to an n-type inversion layer. As a result, the lateral depletion region (Cd, out) and conductive channel (Rs) are formed outside the device, which are functions of substrate doping concentration and the effective oxide charges. The detailed model derivation is discussed in [2]. For this reason, an AC signal applied on the gate would extend outside the device for about a millimeter to a micrometer, affecting measuring results. Based on the model, the effective charges in the SiO2 could be extracted by measuring results. The thicker oxide has more oxide charges, as shown in Fig 6(a). Fig 6(b) and (c) show the modeling results of the Cinv/Cox ratio versus different oxide thicknesses and the Gm/ω-ω plot, which are very close to the experimental results. By simplifying the conductance formula (Gm), Gm reveals an inverse proportional to lateral effective conductance (GLeff) at low frequency (e.g., 10 kHz) and a direct proportional at high frequency (e.g., 1 MHz). Thicker SiO2 devices possess more oxide charges, leading to a greater lateral coupling effect, resulting in a greater GLeff compared to thinner devices. This elucidates the observed variations in Gm-V characteristics at 1 MHz and 10 kHz. Figures 7(a) and (b) display TCAD-simulated C-V and ωm for devices with varying oxide charge densities, confirming that minor changes in oxide charges result in noticeable differences in minority carrier responses in the strong inversion region. Fig 8(a) and (b) show the TCAD simulated results for devices with low doping substrate. For low doping substrates, oxide charges play a much more important role under AC operation.In summary, the study established a correlation between oxide charge densities and thicknesses. The origin of the faster minority carrier response and the peak shift in Gm/ω- ω plot were thoroughly explained and validated by TCAD simulation. Oxide charges were found to play a crucial role, especially in low-doping substrates, offering insights for advanced IC fabrication.[1] E. H. Nicollian and A. Goetzberger, IEEE Transactions on Electron Devices, vol. 12, no. 3, pp. 108-117, 1965.[2] K. C. Chen, K. W. Lin, S. W. Huang, J. Y. Lin, and J. G. Hwu, IEEE Journal of the Electron Devices Society, vol. 10, pp. 960-969, 2022.[3] S. Monaghan et al., IEEE Transactions on Electron Devices, vol. 61, no. 12, pp. 4176-4185, 2014. Figure 1

Impact of Silicon Dioxide Periodic Grating Structure on Electrical Properties of Graphene

Our study breaks away from the conventional focus on 3D transistor structures, aiming to explore the potential of two-dimensional materials. Graphene, a key player of two-dimensional materials, draws significant attention due to its exceptional electrical properties and chemical stability. Rather than delving into the intrinsic properties of graphene, our research focuses on examining the impact that other materials in contact with graphene have on graphene’s behavior. With a thickness of just one atomic layer, graphene's band structure is easily influenced by materials in contact with it, giving rise to the Surface Charge Transfer Doping (SCTD) effect. Our study involves the utilization of e-beam lithography to define 140 nm gratings and RIE to etch into SiO2 substrates. Subsequently, graphene is transferred onto these SiO2 gratings. Within these grating regions, in other words, graphene is supported by SiO2, while other part of the graphene is suspended. By strategically forming alternatively supported/suspended type of graphene in period of 140 nm through these gratings, our aim is to unravel the impact on the electrical characteristics of graphene along both the vertical and horizontal axes. In vertical direction, we measured contact resistance between graphene and metal; in horizontal, we measured the difference of Id-Vg curve caused by the grating structure under graphene channel. This exploration emerges from the quest to harness novel properties in the face of evolving fabrication methodologies.To have 140 nm grating, we chose e-beam lithography in defining the nano grating pattern. Initially, a clean wafer was coated with chromium, and e-beam resist Zep-520A was spin-coated and soft-baked. Subsequently, using e-beam lithography, we defined the periodic pattern. Following this, ICP-RIE was employed for dry etching of chromium, and the resist was removed. Then, ICP-RIE, with chromium as the hard mask, was utilized for dry etching of SiO2. Finally, the chromium was immersed in a chromium etchant solution, resulting in a periodic grating structure with a depth of 100nm on SiO2. This marks the completion of the first part of the fabrication process. In the second part of fabrication process, we transferred graphene, prepared through CVD, onto the SiO2 substrate with periodic gratings defined through etching. We employed optical lithography to define patterns for transmission line method (TLM) measurements. These patterns were aligned with positions defined by e-beam, ensuring that the graphene-metal contact positions precisely coincided with the underlying grating structure. Utilizing TLM, we measured the contact resistance, enabling the study of the impact of the grating on the electrical properties of graphene in the vertical direction. The fabrication flow can be schematically shown in Fig. 1.By using ELS-7000 (E-beam writer) and Oxford ICP-RIE, we successfully achieved ~140 nm grating structure on silicon dioxide with depth of 100nm, which is observed on SEM as shown in Fig. 2. Then we measured the I-V curve by 4200A-SCS and calculated contact resistance by TLM. The preliminary results of the contact resistance measurement are shown in the Fig. 3. The I-V curve shows that as the channel length increases, the total resistance increases, which is aligned with the assumptions of TLM. We can further calculate the contact resistance through the Y-axis intercept of channel length-resistance curve. With the same process, we can explore the electrical variations of graphene with graphene-metal contact resistance and current-voltage relationship. Figure 1

CMOS-Compatible Single-Gated Memtransistor Having 3-D Bulk Channel Embedded with Quantum Well Memory Nodes for Fast Training of Deep Neural Network

Recently, three-terminal synaptic devices having gate, source, and drain electrodes have been actively researched to compensate for the poor reliability of two-terminal synaptic devices such as resistive random access memory (ReRAM) and phase change random access memory (PCRAM)1. Two-terminal devices inherently suffer from read disturbance problems, where the stored resistance state changes gradually during the read process of the artificial neural network2. In addition, two-terminal devices essentially require selection devices for performing the write (program or erase) and read process, which is limited to commercialization because matching of the electrical characteristics between the selection device and the synaptic device was extremely difficult3. Moreover, the training speed of artificial neural networks would degrade due to the constant on/off ratio of conductance of two-terminal synaptic devices.To solve this problem, the memtransistors that can change the conductance range of the channel with gate bias have been reported. However, most of the reported memtransistors employed 2-D materials such as MoS2, WSe2, and SnS2 as a channel layer, which is a limitation for uniform large-area thin film growth4–6. In other words, the memtransistors with a 2-D channel layer do not have CMOS compatibility.In this study, for the first time, we designed a CMOS-compatible single-gated memtransistor having an indium-gallium-zinc-oxide (IGZO) channel embedded with quantum well memory nodes via Au nanoparticles. The quantum well memory nodes were obtained by precisely designing the diameter of Au nanoparticles in the IGZO 3-D bulk channel and SiO2 gate oxide interfaces. In addition, the quantum well memory nodes using Au nanoparticles were investigated by an energy band diagram obtained from ultraviolet photoelectron spectroscopy (UPS) analysis of Au, IGZO, and Al source/drain electrodes. Thereby, the gate-tunable pinched hysteresis loops in the output curve of the designed memtransistor were achieved ranging from -30 to 30 V, which present channel conductance tuning by controlling the amplitude of gate bias. In addition, the gate-tunable synaptic plasticities (i.e., long-term potentiation (LTP) and long-term depression (LTD)) were obtained by changing the amplitude of gate bias from 10.0 to 13.5 V at an incremental of 0.5 V, exhibiting exponential growth of maximum channel conductance depending on the amplitude of gate bias. Finally, we demonstrated the fast training of the hardware-based deep neural network simulation using the gate-tunable synaptic plasticity of the designed memtransistor. The mechanism of single-gated memtransistor having quantum well memory nodes via Au nanoparticles and its application will be presented in detail. Acknowledgement This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIT) (No. RS-2023-00260527) and Institute of Information & communications Technology Planning & Evaluation (IITP) under the artificial intelligence semiconductor support program to nurture the best talents (IITP-(2023)-RS-2023-00253914) grant funded by the Korea government(MSIT)" References Fuller, E. J. et al. Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing. Science (80-. ). 364, 570–574 (2019).Yoon, J., Chang, M. & Khwa, W. Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. Jssc 57, 1–13 (2022).Kim, H. J. et al. Super-Linear-Threshold-Switching Selector with Multiple Jar-Shaped Cu-Filaments in the Amorphous Ge3Se7 Resistive Switching Layer in a Cross-Point Synaptic Memristor Array. Adv. Mater. 2203643, (2022).Lee, H. S. et al. Dual-Gated MoS2 Memtransistor Crossbar Array. Adv. Funct. Mater. 30, 1–12 (2020).Ding, G. et al. Reconfigurable 2D WSe2-Based Memtransistor for Mimicking Homosynaptic and Heterosynaptic Plasticity. Small 17, 1–13 (2021).Rehman, S., Khan, M. F., Kim, H. D. & Kim, S. Analog–digital hybrid computing with SnS2 memtransistor for low-powered sensor fusion. Nat. Commun. 13, 1–8 (2022). Figure 1

(Invited) Electric-Driven Preconcentrating Microfluidic Device for Enhancing Biomolecular Sensing

Preconcentration of biomolecules for detection on microfluidic platforms based on electrical kinetic trapping (EKT) through ion concentration polarization (ICP) has been well developed in the past decade. Biomolecules can be entrapped due to the equilibrium of forces between electro-osmosis and ICP when applying a voltage to the system. In tis study, I will introduce different type of ICPs including theory, mechanism and their limitation. I will also clarify the experimental ICP results based on different microfluidic channel design. A triboelectric nanogenerator (TENG)-driven nanofluidic preconcentrating device that is able to trigger ICP and subsequently cause the EKT of the biomolecules without using a conventional electrical power source was also introduced. The EKT and electrical characteristics of the TENG-based nanofluidic preconcentrator were studied. The preconcentration factors of the device can be found to be ~1000 folds. Several examples of preconcentration device integrating to biosensing techniques are presented in this talk. Some biomarkers are also demonstrated. Further, I will also demonstrate that these biosensors, combining with preconcentrators, can be integrated to a smartphone reader.

Impact of Water-Water Correlation at Suspended Graphene/Water Interface Under Different Electro-Modulated

Graphene-based devices have extensive applications in aqueous environments. The molecular interactions across the graphene sheet significantly impact various devices, although few researches focused on elucidating the interface effects. In this study, we utilize trench structure to make graphene unilaterally and bilaterally suspended in water. The conduction status of both lateral and longitudinal currents (Id, Is, Ig) of graphene was monitored under two suspension scenarios to investigate the changes in interface evolution with the introduction of solvent-solvent interactions. For unilaterally suspended graphene, the current perpendicular to the graphene channel direction remains in the off state. For bilaterally suspended graphene, the current path is formed vertically between the graphene channel and the gate electrode, perpendicular to the direction of the graphene. This experimental setup illustrates the possibilities for exploring interfacial characteristics at the interface between 2D materials and solutions through practical experimentation.The detailed fabrication process of the graphene field-effect-transistor (GFET) device is depicted in Fig. 1. To fabricate the microchannel structure, a microfluidic pattern was generated through photolithography on the SiO2/Si substrate spun with a layer of photoresist. Then, the corresponding microchannel pattern with a thickness of 300 nm SiO2 and 30 μm Si layer was etched by reactive-ion etching (RIE) to form a trench capable of storing water. Afterward, Au electrodes were placed next to the microfluidic channel via evaporation utilizing a shadow mask. The second critical step involves the preparation of graphene. Graphene sheets were grown on a copper foil through the chemical vapor deposition (CVD) method. With the support of PMMA film, physically stacked graphene bilayer graphene was transferred to the target substrate. Ultimately, the suspended bilayer graphene was submerged in acetone for 24 hours to remove the PMMA layer and immersed in isopropanol (IPA) and DI water to clean the residues.According to this device structure, we successfully fabricate the suspension of graphene unilaterally or bilaterally in water. When introducing water through the trench, the bottom surface of the suspended graphene contacts with water molecules, while the upper surface of the suspended graphene is exposed to air. This configuration leads to a unilateral suspension in water (unilateral-suspension GFET). Conversely, when water is introduced through the trench and water is also added above the graphene channel, graphene comes into contact with water on both sides. This configuration results in its bilateral suspension in the water (bilateral-suspension GFET). The electronic transport characteristics of unilateral-suspension GFET and bilateral-suspension GFET were measured by Agilent semiconductor analysis B1500A. The gate voltage was applied to water through an Ag/AgCl electrode. Fig. 2 (a) displays the Raman spectroscopy of suspended graphene on GFET device. The most notable features of the Raman spectrum are the G peak around 1580 cm-1, and the 2D band around 2700 cm-1, which are typical characteristics of graphene. The ID/IG ratio of 0.19 indicates the good quality of the graphene layers. As shown in Fig. 2 (b), the scanning electron microscope (SEM) result of suspended graphene on the GFET device verifies the presence of large-area graphene. The diagram displays a clear demarcation line, facilitating the identification of graphene presence on the substrate. This can also imply the excellent quality of graphene with few defects.The transport behavior of unilateral-suspension GFET and bilateral-suspension GFET are measured individually, as shown in Fig. 3. The sum (ΔI) of The drain current behavior (Id) and source current behavior (Is), and gate current behavior (Ig) are recorded with changed gate voltages (from -1V to +1V) and constant VDS (VDS= 0.1V). For unilateral-suspension GFET, ΔI and Ig keep constant at zero, and there is no conduction path perpendicular to the graphene channel direction. For bilateral-suspension GFET, ΔI and Ig at positive gate voltage are opposite in direction and equal in absolute value, this indicates the formation of an obvious path between the channel and gate electrode. The apparent interfacial evolution is believed to change with the introduction of the other side of water.In conclusion, we compare the electrical characteristics shown by two different suspension situations of graphene-based field effect transistors. There are some interesting results of the conduction path relating to interfacial evolution. This result has potential for chemical sensing or battery application. Furthermore, it can contribute to fundamental research about the interface interaction between suspended graphene and water. Figure 1

(Invited) Organic Memristors for Mimicking Synaptic Plasticity

Since the introduction of a concept of memristor by Leon Chua in 1971 as the fourth fundamental passive component in electronic circuits, and its functional prototype introduced by HP Lab in 2008, research has increasingly concentrated on exploring its application ability in electronic circuits. First, the memristor principles have been exploited in various memory devices within a classical von Neumann computer architecture. The properties of memristor were found particularly suitable for resistive random-access memories (ReRAM).1 Contrary to the classical von Neumann architecture based on the binary logic, advanced methods like neuromorphic computing require an electronic element with continuously varying states depending on previous input signals. The input signal consists of a sequence of voltage spikes that stimulate the device, similarly as a neural synapse does in biological systems. These trains of spikes change the output state of the device continuously to a lower resistance state, mimicking a learning process. Having these functionalities, memristors are considered to be possible building blocks of brain-inspired neuromorphic computing and artificial neural networks.2 Memristors with neurosynaptic functionality take a continuity of resistance values with synaptic weights modulated by the number and frequency of homogeneous spikes. In order to mimic the neural synapse, memristors must exhibit analog properties including non-abrupt switching transitions, memory loss, continuously variable resistance states, and predictable response. We present such functionality on thin films of two kinds of organic materials:(i) A newly synthesized poly(methacrylamide) derivative with carbazole charge transporting group separated from the polymer backbone by an alkyl chain, was synthesized recently and found to behave as a bistable resistive memory.3 Thin films of the polymer, sandwiched between Al and ITO electrodes, exhibit rewritable flash memory behavior with bistable conductivity, with the set switching voltage ranging from 2 to 4.5 V, and the current ON/OFF ratio exceeding 100. The device demonstrates a remarkable lifetime and remains persistent for more than 104 seconds under the static voltage of 0.5 V. The main physical mechanisms driving the resistive switching have been attributed to the electric field-induced reorientation of heterocycles, which modulates charge transport, and trapping/detrapping of charges in localized states within the bulk of the polymer. Memory persistence is strengthened by the physical crosslinking caused by hydrogen bonds between amide and carbonyl groups in the side chains. Depending on the layer thickness, electrode material and applied voltage range the electrical characteristics can change from bistable to analog behavior showing memristive properties.(ii) Ditopic π-conjugated bis-terpyridine (tpy-) ligands form supramolecular structures in which the ligands are interconnected by complexation with metal ions. These molecules offer a low energy operation with improved reproducibility of memristive characteristics. They possess low-lying molecular energy levels and relatively narrow bandgap enabling the low-power consuming resistive switching and longer stability. We used a newly synthesized bis-terpyridine ligands based on 9-phenyl carbazole, Cbz, and its complex with cobalt Co2+ as an active layer of a memristor device. A two-terminal memristor architecture was employed, consisting of the ligand or its cobalt complex deposited on an ITO substrate, and aluminum, gold, or gallium as a top electrode. We show that Cbz as a memristor active layer exhibits an excellent nonvolatile bistable memory behavior, while Co-Cbz exhibits both electronic memory and synaptic plasticity. The ligand exhibited bi-stable conduction and non-volatile memory effect with persistence over 18 hours, while its cobalt complex displayed a synaptic effect characterized by subsequent potentiation and depression cycles. Voltage-induced modulation of synaptic weight was observed with a low applied voltage below 500 mV and short pulse duration below 20 ms. Pair pulse facilitation and pair pulse depression demonstrated significant synaptic weight changes, showing the cobalt complex ability to emulate biological neurons. The operational mechanism was attributed to a combination of the redox effect in the ligand and complex, and to the voltage-induced migration of perchlorate counter ions and subsequent redox processes, altering the metal-to-ligand charge transfer band and changing the conducting state of the active layer.Acknowledgments: The work was financially supported by the Czech Science Foundation, project 24-10384S, and MEYS of the Czech Republic, project LUAUS24032. Strukov, D. B., Snider, G. S., Stewart, D. R. & Williams, R. S. The missing memristor found. Nature 453, 80–83 (2008).Chang, T., Jo, S. H. & Lu, W. Short-term memory to long-term memory transition in a nanoscale memristor. ACS Nano 5, 7669–7676 (2011).Panthi, Y.R, Pfleger, J., Vyprachticky, D., Pandey, A., Thottappali, M.A., Sedenkova, I., Konefal, M. & Foulger, S.H. Rewritable resistive memory effect in poly[N-(3-(9H-carbazol-9-yl)propyl)-methacrylamide] memristor. Mater. Chem. C 11, 17093 (2023).