Efficiency Of RF Power Amplifier Research Articles

EFFICIENCY ANALYSIS OF SWITCHING CONVERTER-MODULATOR

The article discusses methods of highly efficient linear RF power amplifier and transmitter design for future 5G/6G networks. Based on a consideration of various known methods for constructing high-efficiency power amplifiers, the prospects of developments using the envelope elimination and restoration (EER, or Kahn method) and envelope tracking (ET) method are substantiated. The prospects for implementing PWM switching converter-modulator for these methods are assessed. Based on the evaluation calculations performed, it is shown that this structure can potentially be used as an EEP/ET modulator for a number of 5G/6G applications and will have advantages over structures using class AB amplification.

Design of High-efficiency Continuous Class F Doherty Power Amplifier

The high efficiency of the saturation state and rollback state is an important part of the front end of modern wireless communication systems. Improving the efficiency of RF power amplifiers is of great significance for energy saving and amplifier performance. Based on the traditional Doherty power amplifier, the harmonic suppression network is introduced before the fundamental frequency matching, so that the second harmonic impedance and third harmonic impedance can achieve continuous class F impedance matching conditions, and then the saturation efficiency and regression efficiency can be improved without affecting the fundamental wave matching. The results of the simulation show that the saturation efficiency of the Doherty amplifier reaches 73.94%~77.22%. The drain efficiency of back-off 6 dB reaches 61.80%~62.92%. The average saturation drain efficiency is 75.58%, and the average back-off 6 dB drain efficiency is 62.36%.

Comparative criteria for objective evaluation of the efficiency of RF power amplifiers

Objective comparison of radio frequency amplifiers, which are infinitely diverse in their parameters and purpose is a difficult engineering task. For its successful solution it is necessary to define objective criteria that allow to quantify qualitatively and quantitatively the scheme and mode of operation of the amplifier, without this assessment depending on the absolute values of current, voltage, power and parameters of active and passive elements in the electronic circuit.

Characterization of RF Power Amplifier for Narrow and Wide Band Memory Polynomial Implementations

Linearly efficient RF power amplifiers have a tremendous role in wireless communication and radar systems as they lie at the front end of most RF systems. In today’s world of wireless communication, it is not an easy task to design a RF power amplifier that is linearly efficient. There are two main key challenges that one face for making RF power amplifier’s behavior linearly efficient. First is to characterize RF power amplifier’s coefficients smartly. Second is to propose an approach that works on input signal and make its behavior inverse to that of the designed amplifier behavior so that overall response of the system becomes linear. For countering first challenge, most advanced universally accepted algorithms like Memory Polynomial, Generalized Hammerstein, Cross-term Memory Polynomial and Cross-term Hammerstein are implemented to design RF power amplifier models. For countering second challenge, latest DPD algorithms are implemented which make net response of a system linear. The memory models for modelling RF power amplifier are categorized for narrowband and wideband applications. The narrowband power amplifier models include Memory Polynomial and Cross-term Memory Polynomial models whereas wideband power amplifier models include Generalized Hammerstein and Cross-term Hammerstein models. In this paper, various performance indicators like Standard Deviation (SD), Third Order Intercept (TOI), Intermodulation Distortion Products (IMD3), Modulation Error Ratio (MER), Spurious Free Dynamic Range (SFDR) and Error Vector Magnitude (EVM) are used to characterize RF power amplifier for both narrow and wide band applications. The simulation results show that under narrowband applications, Cross-term Memory Polynomial model works best as it has least standard deviation and is also satisfying other performance parameters up to appreciable level with and without DPD algorithm implementation. While for wideband applications, Cross-term Hammerstein model satisfies the performance measuring parameters excellently.

A switching frequency modulated DC-to-DC converter with reduced spurious noise for a RF power amplifier in microwatts transmitters

Varying a supply voltage using a DC-to-DC converter can significantly improve the efficiency of RF power amplifiers (PAs) for low-power RF transceivers. However, intrinsic switching noise from a conventional DC-to-DC converter operating in fixed Pulse-Width Modulation (PWM) can affect the system performance since the spectral components in the switching noise are confined in the fundamental switching frequency and its harmonics. This harmonic noise will have detrimental effects on the performance of the microwatt’s transmitter due to its low output power. Especially for microwatts systems, the minimized size of the inductor will increase the spurious noise due to increased peak-to-peak inductor current. By relocating the spurious noise and reducing peak noise from a switching converter, this paper proposes the technique to prevent high noise spurs in a microwatt transmitter, combining both pseudo-random frequency stepping and monotonic frequency stepping. Both modulation circuits are implemented in CMOS 0.18 µm process and incorporated to achieve the proposed DC-to-DC converter system. The measurement results indicate that the proposed PWM ramp signal modulator with random frequency modulation in a DC-to-DC converter can reduce the peak of the spurious noise-power by 22 dB. Monotonic frequency modulation with various frequency steps reduces the peak of the spurious noise-power by 18 dB.

Highly Efficient Wideband RF Power Amplifier Design for 5G and Beyond

Multiple-in-multiple-out (MIMO) technique is one of the critical techniques for 5G and beyond. Each transmitting channel of the MIMO system must be driven by a power amplifier (PA) accordingly, and the output power levels of these PAs are required to be dynamically adjustable according to the data traffics and the high peak-to-average ratio (PAPR) of the transmit signals. For covering different distances and meeting various required data rates, phased-arrays with 64, 256, and even 1024 elements could be employed together with complex-modulated waveforms, such as 16-, 64-, and 256-QAM in single-carrier and orthogonal frequency-division multiplexing (OFDM) modes used with high PAPR, which creates a strong demand for PAs to have high back-off power efficiency in order to reduce the overall power consumptions of an MIMO system.

History of Class-F and Inverse Class-F Techniques: Developments in High-Efficiency Power Amplification from the 1910s to the 1980s

Today, class-F amplification is a well-established technique for increasing the efficiency of RF power amplifiers (PAs). The increase in efficiency afforded by class F reduces power consumption and increases talk time, both of which are driving forces in the design of RF PAs. The operational efficiency of radio transmitters was of great interest right at the dawn of the development of high-power radiotransmission systems. Many if not most readers will be surprised to learn that the basic concepts of class-F amplification were discovered at the end of the 1910s, just a few years after the first vacuum tube transmitters were developed.

Towards a 15.5W Si-LDMOS Energy Efficient Balanced RF Power Amplifier for 5G-LTE Multi-carrier Applications

In this paper, a 15.5W Si-LDMOS balanced RF power amplifier has been designed using 2.620-2.690GHz frequency band to improve efficiency and linearity for 5G-LTE mobile applications. The amplifier was designed and simulated using large signal Si-LDMOS transistor model to achieve 53% PAE, 41dBm Pout,

Efficient PAPR Reduction in DCT-SCFDMA System Based on Absolute Exponential Companding Technique with Pulse Shaping

Discrete Cosine Transform based Single carrier frequency division multiple access (DCT-SCFDMA) is a prominent technique for providing high data rates in multimedia services. It also provides high Quality of Service to the users by mitigating the fading of signals. But High peak-to-average power ratio (PAPR) is a technical challenge which reduces the efficiency of RF power amplifiers. In this article, a novel joint scheme of PAPR reduction method is proposed and analyzed based on pulse shaping and absolute exponential companding (AEXP) technique. Our method proposes the use of standard raised cosine filter and square root raised cosine filter along with the AEXP companding process separately in DCT-SCFDMA system for different subcarrier mapping techniques e.g. interleaved frequency division multiple access and localized frequency division multiple access. Through extensive simulations, the numerical analysis presents that proposed architecture achieves significant improvements over the existing standard pulse shaping methods when used alone in DCT-SCFDMA system as far as the lowest PAPR is concerned.

A High Efficiency RF Power Amplifier Using Linearity-Enhanced Method in 40nm Standard CMOS Process

A two-stage RF CMOS power amplifier with high linearity for WLAN is presented in this paper.The proposed PA consists of a programmable gain amplifier and a high power stage which is composed of a main amplifier with class AB bias and an auxiliary amplifier with class C bias. To improve the linearity ,an integrated diode linearition circuit provides a compensation mechanism for the input capacitance variation of the active devices,improving the linearity from the gain compressing. Moreover ,based on the un-even bias scheme,the power stage can improve linearity and reduce current consumption in the low power region. In order to demonstrate the feasibility of the technique,two types of PAs have been designed.The improved PA at 3.3V supply voltage,has a 37dB of power gain, 1.1 dBm increase of P,8.3% increase of PAE@Pand dB increase of ACPR for 802.11g WLAN,respectively,as compared with the traditional PA.

A New Topology of Load Network for Class F RF Power Amplifiers

High efficiency RF power amplifiers are increasingly needed in modern mobile communication systems to reduce the battery size and power supply consumption. Class-F RF power amplifiers offer improved efficiency over the conventional class-B power amplifiers by properly controlling the harmonic components of the voltage and current signals at the output terminals of the RF device while driving it to operate as an ON/OFF switch. To do this task, a suitable load network is to be synthesized in order to present the proper harmonic impedances at the output of the RF power transistor. In this paper, a new load network for class F power amplifiers has been introduced and derived analytically. The proposed network consists of a parallel short circuited λ/8 stub, parallel open circuited λ/8 stub, and a T-section lumped-elementtransformer. The benefits of this topology include simplicity of design, controllable bandwidth, and harmonic tuning and impedance transformation at the same time. To confirm the approach of analysis, a 10 W class-F UHF power amplifier circuit has been designed and simulated using a typical Gallium Nitride high electron mobility RF transistor (GaN HEMT) to operate at 500 MHz with the aid of the Advanced Design System (ADS)computer package. The simulated results haveindicated that the circuit gives adc-to-RF efficiency of more than 84 % and a power gain of 11 dB at 500 MHz with an operating bandwidth from 440 to 540 MHz.

Interference cancellation for higher harmonics of supply-modulated efficient RF power amplifier systems

In building highly efficient transmitters of today, one is forced to sacrifice linearity for efficiency. Some of the highest power amplifier efficiency figures are reported by envelope tracking (ET) amplifiers. These amplifiers can generate strong higher-order harmonics, which can lead to interference with receivers operating at the harmonic frequencies. Using non-linear interference cancellation, we can help to remove the interference being caused in those receivers. This paper looks at the problem of modeling the third and second-order harmonic emission from an ET amplifier. It derives the non-linear kernel for estimating such interference. This kernel has been rigorously expanded to show its correlation with the various harmonics and its effectiveness in predicting the harmonic content. We then set up an envelope amplifier test-bench to capture harmonic signal content and cancel it using the derived kernel model. The experiment yields excellent agreement with theory and provides a validation of the system and concept.

Design considerations on wideband envelope termination for high efficiency RF power amplifiers

Design approach of wideband envelope termination (ET) for high efficiency RF power amplifiers (PAs) is discussed, considering power loss subject to design constraints including envelope bandwidth, inductor quality factor, and transistor output impedance. Analysis shows that the optimum ET topology depends on the design constraints. For LTE-advanced transmission with 80 MHz channel bandwidth, a novel wideband ET is designed using an AC-terminated third-order LC filter (LCF-ET), providing 3 dB envelope impedance bandwidth of 150 MHz. Measured results demonstrate 1.75 dB envelope power loss and −39.2 dB normalised root-mean-square error with the LTE envelope signals. For the LTE signal with 10.3 dB peak-to-average power ratio, the average power efficiency of an ideal Class-A RF PA with the LCF-ET prototype is calculated as 33.4% from the measured 1.75 dB envelope power loss, which exceeds 4.7% and 24.0% average power efficiency of conventional Class-A and Class-B PAs without ET.

Split frequency high‐voltage driver for dynamic load modulated RF amplifiers

Dynamic load modulation is a technique for increasing RF power amplifier efficiency by manipulating a tuneable matching network (TMN) between the RF transistor and the antenna in harmony with the envelope of the transmitted signal. Generally, TMNs are based on varactor diodes with control voltage swings approaching 100 V, but future devices are likely to need far greater. The varactor driver amplifier proposed here uses a split frequency architecture to amplify a 3 MHz bandwidth 3GPP 4G long-term evolution envelope signal. Under these conditions, it can produce a peak voltage of 166 V at a power consumption of 0.7 W.

A Fully Integrated High Efficiency RF Power Amplifier for WLAN Application in 40 nm Standard CMOS Process

This paper proposes a CMOS linear power amplifier (PA) design scheme for IEEE 802.11g (WLAN) application. The proposed PA consists of a programmable gain amplifier and a high power stage which is composed of a main amplifier with class AB bias and an auxiliary amplifier with class C bias. Based on the un-even bias scheme, the power stage can improve linearity and reduce current consumption in the low power region. It is fabricated with a TSMC 40 nm standard RF CMOS process. The measurements show that the designed PA reaches a 1 dB gain compression output power of 24.6 dBm and a peak drain efficiency of 38% with a 3.3 V power supply at 2.4 GHz operating frequency range. When the PA was tested with an IEEE 802.11g OFDM signal of 20 MHz channel bandwidth, the obtained -25 dB EVM compliant output power and drain efficiency are 18.5 dBm and 14%, respectively.

A Highly Efficient and Linear Class AB Power Amplifier for RFID Application

Power amplifiers (PAs) are usually the largest consumer of power in the transmitter . Therefore , designing a high efficiency RF power amplifier might be the best solution to cope with the problem of battery lifetime limitations in portable RFID code reader . I n this paper, the designed circuit in Agilent ADS software is implemented using 0.18 μm RFCMOS technology at 3.3 v supply voltage . The measured results indicate that power added efficiency,out put power and power gain of the proposed class AB power amplifier at frequency of 2.4GHz are 35% , 30 dBm and 28dBm.

Papr Reduction of OFDM Signal by Using Combined Hadamard and Modified Meu-Law Companding Techniques

Orthogonal frequency division multiplexing (OFDM) is a technique which gives high quality of service (QOS) to the users by mitigating the fading signals as well as high data rates in multimedia services. However, the peak-to-average power ratio (PAPR) is a technical challenge that reduces the efficiency of RF power amplifiers. In this paper, we propose the combined Hadamard transform and modified meu-law companding transform method in order to lessen the effects of the peak-to-average power ratio of the OFDM signal. Simulation results show that the proposed scheme reduces PAPR compared to other companding techniques as well as the Hadamard transform technique when used on its own.

RF Power Amplifier Efficiency Enhancement by Envelope Injection and Termination for Mobile Terminal Applications

An improved technique to enhance the efficiency of the linear RF power amplifiers (PAs) used in mobile terminal applications is proposed. The baseband load impedance is optimized, and the input envelope, along with the RF signal, is fed to the PA input. The resulting baseband modulation of the drain increases the saturated RF output power for a given dc power consumption. Digital predistortion is implemented to compensate for the linearity degradation. A 1.95-GHz heterojunction GaAs field-effect transistor PA, which in typical bias condition draws 100 mA from an 8.0-V supply and provides maximum power of 28 dBm for a continuous-wave input at 1.95 GHz, exhibits a significant improvement in peak power-added efficiency from 40% to 56% for a two-tone input, from 33% to 42% for an uplink WCDMA with one dedicated physical data channel (DPDCH), and from 27% to 32% for an uplink WCDMA with six DPDCHs.

A Highly Linear and Efficient CMOS RF Power Amplifier With a 2-D Circuit Synthesis Technique

A 2-D circuit synthesis technique (2DCST) is introduced that simultaneously linearizes the AM–AM and AM–PM distortions of CMOS RF power amplifiers (PAs). A class-AB nMOS RF PA fabricated in a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${0.18-}\mu{\hbox {m}}$</tex></formula> CMOS process is reported. With a WCDMA signal, the amplifier achieved 41.6% power-added efficiency (PAE) with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-{\hbox{33-dBc}}$</tex> </formula> single-adjacent channel power ratio (ACPR1) and 38.5% PAE with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-{\hbox{40-dBc}}$</tex></formula> ACPR1 at output powers of 24.9 and 24.0 dBm, respectively. This state-of-the-art linearity and efficiency performance is comparable to that of GaAs HBT linear RF PAs. The 2DCST is applicable to a broad range of analog circuits and other semiconductor technologies.

A Linear Assisted DC/DC Converter for Envelope Tracking and Envelope Elimination and Restoration Applications

In recent years, there has been a great deal of focus on the development of fast and efficient dc/dc converters in an effort to follow the envelope of communication signals for increasing the efficiency of RF power amplifiers by using techniques such as envelope tracking and envelope elimination and restoration. However, the bandwidth and slew rate required by modern communication signals are higher than the maximum ones achievable by switching dc/dc converters made for this purpose. The slew rate of these switching dc/dc converters can be improved by combining it with the use of a linear stage, thus establishing a trade-off between slew rate and overall efficiency. This paper presents a simple way of combining the use of both a switching dc/dc converter, the multiple input buck converter, and a linear stage to obtain slew rates above 100 V/μs, with a moderate decrease in the overall efficiency [81% efficiency tracking the envelope of an enhanced data rates for GSM evolution (EDGE) standard signal]. Finally, a prototype of the complete system (including the digital control for both stages) is presented in this paper.