Abstract
A two-stage RF CMOS power amplifier with high linearity for WLAN is presented in this paper.The proposed PA consists of a programmable gain amplifier and a high power stage which is composed of a main amplifier with class AB bias and an auxiliary amplifier with class C bias. To improve the linearity ,an integrated diode linearition circuit provides a compensation mechanism for the input capacitance variation of the active devices,improving the linearity from the gain compressing. Moreover ,based on the un-even bias scheme,the power stage can improve linearity and reduce current consumption in the low power region. In order to demonstrate the feasibility of the technique,two types of PAs have been designed.The improved PA at 3.3V supply voltage,has a 37dB of power gain, 1.1 dBm increase of P,8.3% increase of PAE@Pand dB increase of ACPR for 802.11g WLAN,respectively,as compared with the traditional PA.
Highlights
Due to low cost and ease of integration complimentary metal oxide semiconductor(COMS) is becoming the technology of choice for most wireless application
The past few years have seen a lot of advancement in CMOS circuit design as well as device technology,which have made it possible to implement RF circuit blocks in CMOS with performance just as good as any other technology
RF blocks such as low noise amplifiers(LNA),mixers and voltage-controlled oscillators(VCO) are readily implemented in CMOS.RF power amplifiers (PAs) are a major roadblock in these efforts to create highly integrated system-on-chip,due to both the low breakdown voltage of the transistor and lossy substrate associated CMOS technology.the PAs for high data rate wireless communication systems have been required high efficiency and linearity at the back-off power levels to efficiently amplify a multiplexing signal
Summary
Due to low cost and ease of integration complimentary metal oxide semiconductor(COMS) is becoming the technology of choice for most wireless application. RF blocks such as low noise amplifiers(LNA),mixers and voltage-controlled oscillators(VCO) are readily implemented in CMOS.RF power amplifiers (PAs) are a major roadblock in these efforts to create highly integrated system-on-chip,due to both the low breakdown voltage of the transistor and lossy substrate associated CMOS technology.the PAs for high data rate wireless communication systems have been required high efficiency and linearity at the back-off power levels to efficiently amplify a multiplexing signal. The output-stage is composed of a main amplifier with class AB bias and an auxiliary amplifier with class C bias,which can improve linearity and reduce current consumption in the low power region.In particular,an integrated diode linearization technology provides the compensation mechanism for the input capacitance variation of the active devices to enhance the linearity of the CMOS PAs[1]. This paper describes some improved PA design techniques to realize high power and high efficiency in a small area using the standard 40nm CMOS technology.
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