Efficient Application Mapping Research Articles

Efficient application mapping approach based on grey wolf optimization for network on chip

In modern chip designs with multiple processors, network-on-chip (NoC) has emerged as a critical solution, offering scalability, flexibility, modularity, and efficiency. However, a significant challenge in application mapping is minimizing communication costs as they directly affect performance and energy consumption. Although several mapping algorithms have been developed, they often suffer from complexity, suboptimal performance, and slow convergence. To address these challenges, this paper proposes a novel approach for mapping using the grey wolf optimization (GWO) technique inspired by nature. The proposed GWO-based mapping approach for NoC (GNoC) is augmented with an effective clustering-based initial mapping strategy, further enhancing its capabilities. Furthermore, a second heuristic algorithm is introduced, incorporating a modified GWO method with polynomial regression (GNoC-PR). This modification optimizes the runtime efficiency and enhances the overall mapping quality. The proposed method was evaluated through comprehensive simulations and compared with state-of-the-art solutions. The results demonstrate that the proposed algorithm outperforms existing methods in several key metrics, including a power consumption reduction of 19.7%, energy efficiency improvement of 17%, and a significant 40% decrease in computational overhead on average. To validate the effectiveness of our mapping technique, we evaluated both embedded and synthetic applications, considering various metrics such as communication cost, average network latency, and power consumption.

The CTH Network: An NoC Platform for Scalable and Energy Efficient Application Mapping Solution

Multi-threaded design of the applications has given a new dimension to the execution concurrency. The Network-on-Chip (NoC) infrastructure has evolved as the communication backbone in multiprocessor System-on-Chips (MPSoCs) to exploit Thread-Level Parallelism (TLP). Mapping the threads of various applications on the processing cores is crucial in utilizing the resources of a many-core system. An application's performance depends primarily on the mapping strategy. However, the performance of an application gets influenced significantly by the underlying network architecture of the NoC. The present work proposes a run-time application mapping technique based on the Cube-Tree-Hybrid (CTH) topology focusing on the traffic load balancing across the network. The mapping overhead decreased significantly by exploiting the low network diameter of CTH with its high scalability and path diversity, projecting a 31% reduction in normalized execution time over the prevalent algorithms on the existing mapping platforms. Rigorous experimentation with varying application and network sizes is carried out across mesh, ZMesh, torus, and Mest-of-Tree (MoT) networks. The experimental observations project that the proposed algorithm results in sustainable application performance with 15%-21% gain in the overall energy consumption over the existing state-of-the-art techniques across various benchmark workloads.

AI-PiM—Extending the RISC-V processor with Processing-in-Memory functional units for AI inference at the edge of IoT

The recent advances in Artificial Intelligence (AI) achieving “better-than-human” accuracy in a variety of tasks such as image classification and the game of Go have come at the cost of exponential increase in the size of artificial neural networks. This has lead to AI hardware solutions becoming severely memory-bound and scrambling to keep-up with the ever increasing “von Neumann bottleneck”. Processing-in-Memory (PiM) architectures offer an excellent solution to ease the von Neumann bottleneck by embedding compute capabilities inside the memory and reducing the data traffic between the memory and the processor. But PiM accelerators break the standard von Neumann programming model by fusing memory and compute operations together which impedes their integration in the standard computing stack. There is an urgent requirement for system-level solutions to take full advantage of PiM accelerators for end-to-end acceleration of AI applications. This article presents AI-PiM as a solution to bridge this research gap. AI-PiM proposes a hardware, ISA and software co-design methodology which allows integration of PiM accelerators in the RISC-V processor pipeline as functional execution units. AI-PiM also extends the RISC-V ISA with custom instructions which directly target the PiM functional units resulting in their tight integration with the processor. This tight integration is especially important for edge AI devices which need to process both AI and non-AI tasks on the same hardware due to area, power, size and cost constraints. AI-PiM ISA extensions expose the PiM hardware functionality to software programmers allowing efficient mapping of applications to the PiM hardware. AI-PiM adds support for custom ISA extensions to the complete software stack including compiler, assembler, linker, simulator and profiler to ensure programmability and evaluation with popular AI domain-specific languages and frameworks like TensorFlow, PyTorch, MXNet, Keras etc. AI-PiM improves the performance for vector-matrix multiplication (VMM) kernel by 17.63x and provides a mean speed-up of 2.74x for MLPerf Tiny benchmark compared to RV64IMC RISC-V baseline. AI-PiM also speeds-up MLPerf Tiny benchmark inference cycles by 2.45x (average) compared to state-of-the-art Arm Cortex-A72 processor.

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the high-performance constraints of composite embedded applications is on the rise. This leads to the realization of efficient mapping approaches for such complex applications. The significance of efficient application mapping approaches has increased ever since the embedded applications have become more complex and performance-oriented. This paper presents the detailed comparative analysis and categorization of application mapping approaches with current trends in NoC design implementation. These approaches target to improve the performance of the whole system by optimizing communication cost, energy, power consumption, and latency. Apart from the categorization of the discussed approaches, comparison of communication cost, power, energy, and latency of the NoC system carried out on real applications like VOPD and MPEG4. Moreover, the best technique identified in each category based on the evaluation of performance results.

Performance constrained multi-application network on chip core mapping

This paper proposes the Bat mapping algorithm for efficient application mapping on NoC platform. This approach was assessed by applying it to various benchmark applications. Experimental results revealed that the Bat mapping algorithm has two major contributions compared with existing algorithms: (1) It enables dynamic mapping and efficiently identifies the most favorable mapping system. (2) The simulation tests indicated that the Bat algorithm exhibits higher performance.

KBMA: A knowledge‐based multi‐objective application mapping approach for 3D NoC

Due to increased demands for communication at low power, an efficient application mapping has become vital in the area of network on chip (NoC). Optimisation of architectural structure in on-chip design is essential to maximise the performance of the network and minimise the cost functions. To address this issue, a knowledge-based memetic algorithm (KBMA) is proposed for 3D NoC for successful mapping with standard network topologies. The proposed KBMA adopts power, area and delay as a cost function for an effective mapping. The competence of the proposed method is verified through comparison with other natural inspired algorithms like particle swarm optimisation and genetic algorithm. The presented work is validated through four case studies which include real application benchmarks of NoC and random generated benchmarks using test graph for free.

Efficient Mapping of Applications for Future Chip-Multiprocessors in Dark Silicon Era

The failure of Dennard scaling has led to the utilization wall that is the source of dark silicon and limits the percentage of a chip that can actively switch within a given power budget. To address this issue, a structure is needed to guarantee the limited power budget along with providing sufficient flexibility and performance for different applications with various communication requirements. In this article, we present a general-purpose platform for future many-core Chip-Multiprocessors (CMPs) that benefits from the advantages of clustering, Network-on-Chip (NoC) resource sharing among cores, and power gating the unused components of clusters. We also propose two task mapping methods for the proposed platform in which active and dark cores are dispersed appropriately, so that an excess of power budget can be obtained. Our evaluations reveal that the first and second proposed mapping mechanisms respectively reduce the execution time by up to 28.6% and 39.2% and the NoC power consumption by up to 11.1% and 10%, and gain an excess power budget of up to 7.6% and 13.4% over the baseline architecture.

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

In this paper, an efficient application mapping approach is proposed for the co-optimization of reliability, communication energy, and performance (CoREP) in network-on-chip (NoC)-based reconfigurable architectures. A cost model for the CoREP is developed to evaluate the overall cost of a mapping. In this model, communication energy and latency (as a measure of performance) are first considered in energy latency product (ELP), and then ELP is co-optimized with reliability by a weight parameter that defines the optimization priority. Both transient and intermittent errors in NoC are modeled in CoREP. Based on CoREP, a mapping approach, referred to as priority and ratio oriented branch and bound (PRBB), is proposed to derive the best mapping by enumerating all the candidate mappings organized in a search tree. Two techniques, branch node priority recognition and partial cost ratio utilization, are adopted to improve the search efficiency. Experimental results show that the proposed approach achieves significant improvements in reliability, energy, and performance. Compared with the state-of-the-art methods in the same scope, the proposed approach has the following distinctive advantages: 1) CoREP is highly flexible to address various NoC topologies and routing algorithms while others are limited to some specific topologies and/or routing algorithms; 2) general quantitative evaluation for reliability, energy, and performance are made, respectively, before being integrated into unified cost model in general context while other similar models only touch upon two of them; and 3) CoREP-based PRBB attains a competitive processing speed, which is faster than other mapping approaches.

Automatic complex instruction identification for efficient application mapping onto application-specific instruction set processors

Custom instruction identification is an essential part in designing efficient application-specific instruction set processors (ASIPs). Basically, the identification process consists of profiling the application of interest to find the frequently executed sub-sets of basic operations that can be implemented as a single custom instruction in the ASIP datapath. This accelerates the execution of the given application, or even of a set of applications of the same domain. However, a naive ad hoc instruction set customization process may not result in a significantly improved performance with low circuit area and energy consumption footprints. In this work, we propose and discuss a novel efficient instruction set customization method implemented as an automatic tool that is able to identify promising custom instruction candidates for a set of relevant benchmark applications. The proposed method formulates the common subgraph enumeration problem as a maximum clique-enumeration problem, with a twofold novel contribution: accounting for the connectivity aspect; and the graph associativity detection. The performance results are provided for the usage of the proposed tool for a configurable commercially available VLIW-ASIP for configurations of up to three augmented issue-slots, achieving a speedup of up to 54 % for the ray-tracing application. Circuit area and energy consumption results based on the TSMC 65 nm technology are also presented. The obtained results are compared to those reported in related works.

Compiling Scilab to high performance embedded multicore systems

The mapping process of high performance embedded applications to today’s multiprocessor system-on-chip devices suffers from a complex toolchain and programming process. The problem is the expression of parallelism with a pure imperative programming language, which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from different domains. The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from a high level of abstraction. The holistic solution of the ALMA toolchain allows the complexity of both the application and the architecture to be hidden, which leads to better acceptance, reduced development cost, and shorter time-to-market. Driven by the technology restrictions in chip design, the end of exponential growth of clock speeds and an unavoidable increasing request of computing performance, ALMA is a fundamental step forward in the necessary introduction of novel computing paradigms and methodologies.

Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs

Modern embedded systems need to support multiple time-constrained multimedia applications that often employ multiprocessor-systems-on-chip (MPSoCs). Such systems need to be optimized for resource usage and energy consumption. It is well understood that a design-time approach cannot provide timing guarantees for all the applications due to its inability to cater for dynamism in applications. However, a runtime approach consumes large computation requirements at runtime and hence may not lend well to constrained-aware mapping. In this article, we present a hybrid approach for efficient mapping of applications in such systems. For each application to be supported in the system, the approach performs extensive design-space exploration (DSE) at design time to derive multiple design points representing throughput and energy consumption at different resource combinations. One of these points is selected at runtime efficiently, depending upon the desired throughput while optimizing for energy consumption and resource usage. While most of the existing DSE strategies consider a fixed multiprocessor platform architecture, our DSE considers a generic architecture, making DSE results applicable to any target platform. All the compute-intensive analysis is performed during DSE, which leaves for minimum computation at runtime. The approach is capable of handling dynamism in applications by considering their runtime aspects and providing timing guarantees. The presented approach is used to carry out a DSE case study for models of real-life multimedia applications: H.263 decoder, H.263 encoder, MPEG-4 decoder, JPEG decoder, sample rate converter, and MP3 decoder. At runtime, the design points are used to map the applications on a heterogeneous MPSoC. Experimental results reveal that the proposed approach provides faster DSE, better design points, and efficient runtime mapping when compared to other approaches. In particular, we show that DSE is faster by 83% and runtime mapping is accelerated by 93% for some cases. Further, we study the scalability of the approach by considering applications with large numbers of tasks.

MpAssign: a framework for solving the many‐core platform mapping problem

SUMMARYMany‐core platforms, providing large numbers of parallel execution resources, emerge as a response to the increasing computation needs of embedded applications. A major challenge raised by this trend is the efficient mapping of applications on parallel resources. This is a nontrivial problem because of the number of parameters to be considered for characterizing both the applications and the underlying platform architectures. Recently, several authors have proposed to use multi‐objective evolutionary algorithm to solve this problem within the context of mapping applications on network‐on‐chips. However, these proposals have several limitations: (1) only few metaheuristics are explored (mainly Nondominated Sorting Genetic Algorithm II and Strength Pareto Evolutionary Algorithm 2), (2) only few objective functions are provided, and (3) they only deal with a small number of the application and architecture constraints. In this paper, we propose a new framework that avoids all of the problems cited previously. Our framework is implemented on top of the jMetal framework, which offers an extensible environment. Our framework allows designers to (1) explore several new metaheuristics, (2) easily add a new objective function (or to use an existing one), and (3) take into account any number of architecture and application constraints. The paper also presents experiments illustrating how our framework is applied to the problem of mapping streaming applications on an NoC‐based many‐core platform. Our results show that several new metaheuristics outperform the classical multi‐objective metaheuristics such as Nondominated Sorting Genetic Algorithm II and Strength Pareto Evolutionary Algorithm 2. Moreover, a parallel multi‐objective evolutionary algorithm is implemented in our framework in order to increase the explored space of solutions by simultaneously running several metaheuristics. Copyright © 2011 John Wiley & Sons, Ltd.

A holistic approach for tightly coupled reconfigurable parallel processors

New standards in signal, multimedia, and network processing for embedded electronics are characterized by computationally intensive algorithms, high flexibility due to the swift change in specifications. In order to meet demanding challenges of increasing computational requirements and stringent constraints on area and power consumption in fields of embedded engineering, there is a gradual trend towards coarse-grained parallel embedded processors. Furthermore, such processors are enabled with dynamic reconfiguration features for supporting time- and space-multiplexed execution of the algorithms. However, the formidable problem in efficient mapping of applications (mostly loop algorithms) onto such architectures has been a hindrance in their mass acceptance. In this paper we present (a) a highly parameterizable, tightly coupled, and reconfigurable parallel processor architecture together with the corresponding power breakdown and reconfiguration time analysis of a case study application, (b) a retargetable methodology for mapping of loop algorithms, (c) a co-design framework for modeling, simulation, and programming of such architectures, and (d) loosely coupled communication with host processor.

Micro-Task Processing in Heterogeneous Reconfigurable Systems

New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices (e.g., FPGAs). One of the new promising architectures are Configurable System-on-Chip (CSoC) solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller (mTC) unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results are given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.

Efficient Mapping of Applications on Cache Based Multiprocessors

Cache coherent multiprocessors have become popular in recent times because they reduce the memory latency. It is important to accurately estimate the intertask communication time in order to efficiently map the program tasks onto the processors. Computing the communication requirements from program characteristics in the presence of cache coherence protocols is difficult. In this paper we present a technique to compute the communication times of programs on cache coherent distributed shared memory systems. Simulated annealing is used to obtain near optimal mappings of program tasks onto processors. The techniques are demonstrated using a Sequent Balance multiprocessor and the Jacobi iteration problem. The estimated communication costs agree with the measured values within 15%. It is also shown that taking the effects of cache coherence into account results in more efficient mapping of applications.