Hardware Utilization Efficiency Research Articles

Trinetra: a solution to handle cross-VM time-driven attack

The efficient utilization of hardware and software resources plays a vital role in a high-performance computing environment. Where on the one side, a shared pool of resources facilitates faster processing with limited resources, this mechanism also widens the scope of many kinds of security attacks on the other side. Side-channel attack (SCA) is one such attack where methods to monitor the activity of exploited shared resource is carried out to extract the private key. One such SCA, branch prediction analysis attack, launched with time-driven attack (TDA) method is considered in this paper. With the consideration of the virtualization environment, proposal of an algorithm Trinetra, to detect the presence of cross-VM TDA, is the primary focus of our paper. We have tested the performance of Trinetra with experimental analysis in addition to the attack simulation. Performance evaluation has found the Trinetra very effective with negligible performance overhead.

E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory

Long Short-Term Memory (LSTM) and its variants have been widely adopted in many sequential learning tasks, such as speech recognition and machine translation. Significant accuracy improvements can be achieved using complex LSTM model with a large memory requirement and high computational complexity, which is time-consuming and energy demanding. The low-latency and energy-efficiency requirements of the real-world applications make model compression and hardware acceleration for LSTM an urgent need. In this paper, several hardware-efficient network compression schemes are introduced first, including structured top- $k$ pruning, clipped gating, and multiplication-free quantization, to reduce the model size and the number of matrix operations by 32 $\times $ and 21.6 $\times $ , respectively, with negligible accuracy loss. Furthermore, efficient hardware architectures for accelerating the compressed LSTM are proposed, which support the inference of multi-layer and multiple time steps. The computation process is judiciously reorganized and the memory access pattern is well optimized, which alleviate the limited memory bandwidth bottleneck and enable higher throughput. Moreover, the parallel processing strategy is carefully designed to make full use of the sparsity introduced by pruning and clipped gating with high hardware utilization efficiency. Implemented on Intel Arria10 S $\times $ 660 FPGA running at 200MHz, the proposed design is able to achieve 1.4–2.2 $\times $ energy efficiency and requires significantly less hardware resources compared with the state-of-the-art LSTM implementations.

A self-healing strategy with fault-cell reutilization of bio-inspired hardware

The self-healing strategy is a key component in designing the bio-inspired embryonics circuit with the structure of cell arrays. However, the existing self-healing strategies of embryonics circuits mainly focus on permanent faults inside the modules of cells such as the function module and the configuration register, while little attention is paid to transient faults. From the point of view of obtaining high efficiency of hardware utilization, it would be a huge waste of hardware resources by permanent elimination when a cell only suffers a transient fault which can be repaired by a configuration mechanism. A new self-healing strategy, the Fault-Cell Reutilization Self-healing Strategy (FCRSS) which presents a method for reusing transient fault cells, is proposed in this paper. The circuit structures of all the modules in the cells are described in detail. In the new strategy, two processes of elimination and reconfiguration are combined. Within the process of fault-cell elimination, cells with transient faults in the embryonics circuit array could be reused simultaneously to replace the functions of the cells on their left side in the same row. Therefore, transient fault-cells in a transparent state can be reconfigured to realize the fault-cell reutilization. Finally, a circuit simulation, resource consumption, a reliability analysis and a detailed normalization analysis are presented. The FCRSS can improve the hardware utilization rate and system reliability at the expense of a small amount of hardware resources and reconfiguration time. Following the conclusion, the method of determining the optimal self-healing strategy is presented according to the environmental conditions.

High speed multi-channel data acquisition technique for efficient hardware utilization using quad data rate approach

Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data received are processed in real-time environment. This paper proposes a novel Data Acquisition (DAQ) technique for better resource utilization with less power consumption. Present work has designed and compared advanced Quad Data Rate (QDR) technique with traditional Dual Data Rate (DDR) technique in terms of resource utilization and power consumption of Field Programmable Gate Array (FPGA) hardware. Xilinx ISE is used to verify results of FPGA resource utilization by QDR with state of the art DDR approach. The paper ratiocinates that QDR technique outperforms traditional DDR technique in terms of FPGA resource utilization.

Performance of a high-throughput tracking processor implemented on Stratix-V FPGA

Abstract Two of the biggest challenges for future HEP experiments at hadron colliders are triggering and track reconstruction of high-multiplicity events, where collisions have multiple primary vertices. The highly-non-linear scaling of computing power required for these tasks encourages the adoption of non-traditional, specialized architectures. Amongst them, the “artificial retina” approach, inspired by the architecture of the vision system in the living brain, promises large efficiency of hardware utilization, low-power and low-latency when implemented in state-of-art FPGA devices. The INFN-RETINA project has been a 3-year effort dedicated to investigate the potential of that approach in a real-time tracking processor at Level-0 of the LHC HEP experiments. We present results from studies performed on a prototype system capable of carrying out track reconstruction in a generic 6-layer silicon-strip detector with sub- μ s latency at an event rate in excess of 30 MHz, and how a large-scale system can be implemented on multiple boards interconnected with high-speed optical links. Possible applications to real experimental environments will be also discussed.

Decoupled MapReduce for Shared-Memory Multi-Core Architectures

Modern multi-core processors exhibit high integration densities, e.g., up to several tens of cores. Multiple programming frameworks have emerged to facilitate the development of highly parallel applications. The MapReduce programming model, after having demonstrated its usability in the area of distributed computing systems, has been adapted to the needs of shared-memory multi-processors showing promising results in comparison with conventional multi-threaded libraries, e.g., pthreads. In this paper we enhance the traditional MapReduce architecture by decoupling the map and combine phases in order to boost parallel execution. We show that combiners’ memory intensive features limit the system’s degree of parallelism, thus resulting in sub-optimal hardware utilization, leaving space for further performance improvements. The proposed decoupled MapReduce architecture is evaluated into a NUMA server platform, showing that the adoption of the De-MapR runtime enables more efficient hardware utilization and competent run-time improvements. We demonstrate that the proposed solution achieves execution speedups of up to 2.46x compared to a state-of-the-art, shared-memory MapReduce library.

Image encoder architecture design using dual scan based DWT with vector quantization

Vector quantizer block requires additional hardware resources, it was demonstrated that the codebook generated by coding the residual block makes the image codec more robust. This efficient algorithm is mainly based on flipping technique. First, a three level DWT is performed on the original image resulting in ten separate sub bands. These sub bands are then vector quantized. To implement a hardware efficient and modular architecture with a very simple control path this proposed method is presented. To minimize the critical path to one multiplier delay and to achieve 100% hardware utilization efficiency, the serial operation is optimized using parallel computation in advance with pipeline operation of independent path. This algorithm uses only five transposition register and it is repeatable architecture. Data path can be reduced to six multipliers and eight adders by folding this architecture without affecting the critical path.

A LITERATURE REVIEW: EFFICIENT VM MIGRATION TECHNIQUES FOR ENERGY REDUCTION IN CLOUD COMPUTING

Broadly speaking cloud computing is nothing but a highly ‘utilitarian’ orientation of IT services where users benefited on a pay-as-you go basis. In a way it enables the hosting of pervasive applications from consumer, scientific and business domain. We expect all electronic gadgetry to be ‘energy efficient’ to possibly achievable limits. So our data centers hosting cloud application must be cost effective and the same time should avoid undue burden of carbon footprint. While excising economy on power consumption by (data center) outmost care needs to be taken so that it never at the cost services provided to end user i.e. SLA violation must be kept as low as possible. Virtualization technology is one of the key features in cloud data centers that can improve the efficiency of hardware utilization through resource sharing, migration, and consolidation of workloads. In this paper we shall cover VM Migration Algorithms for energy reduction in cloud computing along with other novel techniques.

UniCNN: A Pipelined Accelerator Towards Uniformed Computing for CNNs

Convolutional neural networks (CNNs) have been widely applied for image recognition, face detection, and video analysis because of their ability to achieve accuracy close to or even better than human level perception. However, different features of convolution layers and fully connected layers have brought many challenges to the implementation of CNN on FPGA platforms, because different accelerator units must be designed to process the whole networks. In order to overcome this problem, this work proposes a pipelined accelerator towards uniformed computing for convolutional neural networks. For the convolution layer, the accelerator first repositions the input features into matrix on-the-fly when they are stored to FPGA on-chip buffers, thus the computation of convolution layer can be completed through matrix multiplication. For the fully connected layer, the batch-based method is used to reduce the required memory bandwidth, which also can be completed through matrix multiplication. Then a pipelined computation method for matrix multiplication is proposed to increase the throughput and also reduce the buffer requirement. The experiment results show that the proposed accelerator surpasses CPUs and GPUs platform in terms of energy efficiency. The proposed accelerator can achieve the throughput of 49.31 GFLOPS, which is done using only 198 DSP modules. Compared to the state-of-the-art implementatuion, our accelerator has better hardware utilization efficiency.

Design and efficient hardware implementation schemes for non-Quasi-Cyclic LDPC codes

The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic (NQC) Low-Density Parity-Check (LDPC) codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing (MOMP) algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing (OMP) technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-dB coding gain for Binary PhaseShift Keying (BPSK) in an Additive White Gaussian Noise (AWGN) channel, the decoder with the proposed scheme achieves a 23.8%-52.6% reduction in logic utilization per Mbps and a 29.0%-90.0% reduction in message-memory bits per Mbps.

Design and implementation of a highly efficient fractional motion estimation for the HEVC encoder

This paper presents the VLSI architecture and implementation of the highly efficient fractional motion estimation (FME) for High Efficiency Video Coding (HEVC) systems. In this design, the processing sequence of input pixels is highly optimized so that large parts of the hardware resources in the interpolator circuit are shared and the area complexity is greatly reduced. In order to further enhance the efficiency of hardware utilization and to achieve high throughput, the sum of absolute transformed differences circuit is realized using a pipelined time-multiplexing scheme, and the hardware-sharing structure is utilized to reduce the required computation components. Furthermore, comparing to the literature based on HEVC systems, this design enhances the rate-distortion performance by supporting more prediction modes. The proposed design has been synthesized, placed, and routed through cell-based design flow using TSMC 90-nm technology. The post-layout estimations show that, occupying the area complexity of 525.4 kGE, the presented FME architecture achieves 39 frames per second (fps) with resolution of 3840 × 2160 and 29 fps with resolution of 7680 × 4320. In addition, comparing to the prior art that supports 30 fps and the same number of prediction modes, this design achieves a 2 × improvement of hardware efficiency.

AM : Towards A Hardware Unix Accelerator for Many-Cores

This article advocates the use of new architectural features commonly found in many-cores to replace the machine model underlying Unix-like operating systems. We present a general Abstract Many-core Machine Model (AM $^3$ ), a proof-of-concept implementation and first evaluation results in the context of an emerging many-core, hardware multi-threaded architecture without support for interrupts. Our proposed approach makes it possible to reuse off-the-shelf multithreaded/multiprocess software on massively parallel architectures, without need to change code to use custom programming models like CUDA or OpenCL. Benefits include higher hardware utilization, higher performance and higher energy efficiency for workloads common to general-purpose platforms, such as in datacenters and clouds. The benefits also include simpler software control over the hardware platform, an enabling factor for the further evolution of parallel programming languages.

Artificial Bee Colony with Map Reducing Technique for Solving Resource Problems in Clouds

Background/Objectives: Overseeing resources at mega scale while giving performance isolation and efficient utilization of basic hardware is a key test for any cloud management software. Aside from scalability issue, a cloud-level resource management layer requirements to settle the heterogeneity of frameworks, compatibility imperatives between virtual machines and basic hardware, islands of resources made because of storage and network connectivity and restricted scale of storage resources. Methods/Statistical Analysis: Upshots prospects promising optimizable brooks initiated probe in various filed, in this work we projected an effectual topology for solving the resource model for resource problem solution. Deployment of optimization algorithm opted for multi objective problem is Artificial Bee Colony Algorithm (ABC) which delivered best optimized result and less computation time is utilized to unfurl the determined objective, upshots of the proposition topology has depicted promising and effectual results and minimized computational exertion. Findings: In our proposed method, the execution time is reduced largely when compared to the existing method. Applications/Improvements: Optimization of cloud computing resource utilization.

ANALYSIS OF EFFECTS OF USING 9/7 WAVELET COEFFICIENTS IN MULTI-RESOLUTION ANALYSIS

Conventional distributed arithmetic (DA) is popular in field programmable gate array (FPGA) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, we describe high speed area efficient 1-D discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA) Technique. Being area efficient architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. This architecture supports any size of image pixel value and any level of decomposition. The parallel structure has 100% hardware utilization efficiency.

A Study on Security Vulnerability on Cloud Platforms

Cloud computing provides an in-built platform to the users with easy and on-demand access to different system level services for creating virtual machines (VM) with efficient utilization of hardware, computing and network resources. This allows users to remotely execute large number of applications across various domains such as, health-care, utility services, e-governance, etc. There are different cloud operating platforms for creation and management of virtual machines through various system or application services. For example, openstack, oracle virtualbox, Microsoft HyperV are widely used operating platform. Virtual machine migration (VMM) is one of such important system services that used for smooth the progress of system maintenance, load management, fault tolerance, secure and safe service offerings. Virtual Machine live migration service transfers an active VM from one physical machine to another across different data centres. It involves a sequence of operations in iteration for migrating execution context of a VM to the destination machine. These operations are dependent on schedule, availability of resources and overall timing constraints. On the other hand, the migration process involves transferring the control data over a communication channel with a shared storage. Due to the above mentioned complexities of VM migration process, any security failures during the migration may cause transfer of incorrect VM instance to a data centre and which in turn may lead to exposure of the data centre to the attackers. This may be manifested as catastrophic system failure, degradation of system performance, load balancing and in long run may result collapse of the data centre. In this paper we studied various security vulnerability in different cloud platforms. These vulnerability will help the security developers to design a secured cloud platform.

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English

High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

In this paper, three hardware efficient architectures to perform multi-level 2-D discrete wavelet transform (DWT) using lifting (5, 3) and (9, 7) filters are presented. They are classified as folded multi-level architecture (FMA), pipelined multi-level architecture (PMA), and recursive multi-level architecture (RMA). Efficient FMA is proposed using dual-input Z-scan block (B1) with 100% hardware utilization efficiency (HUE). Modular PMA is proposed with the help of block (B1) and dual-input raster scan block (B2) with 60% to 75% HUE. Block B1 and B2 are micro-pipelined to achieve critical path as single adder and single multiplier for lifting (5, 3) and (9, 7) filters, respectively. The clock gating technique is used in PMA to save power and area. Hardware-efficient RMA is proposed with the help of block (B1) and single-input recursive block (B3). Block (B3) uses only single processing element to compute both predict and update; thus, 50% multipliers and adders are saved. Dual-input per clock cycle minimizes total frame computing cycles, latency, and on-chip line buffers. PMA for five-level 2-D wavelet decomposition is synthesized using Xilinx ISE 10.1 for Virtex-5 XC5VLX110T field-programmable gate array (FPGA) target device (Xilinx, Inc., San Jose, CA, USA). The proposed PMA is very much efficient in terms of operating frequency due to pipelining. Moreover, this approach reduces and totals computing cycles significantly as compared to the existing multi-level architectures. RMA for three-level 2-D wavelet decomposition is synthesized using Xilinx ISE 10.1 for Virtex-4 VFX100 FPGA target device.

CRANarch: A feasible processor micro-architecture for Cloud Radio Access Network

Cloud Radio Access Network (C-RAN) becomes a promising infrastructure, which can improve hardware resource utilization of traditional Radio Access Network (RAN). For C-RAN, data centers are essential hardware platform, and these data centers are universally equipped with general commercial multi-core processors which are not designed for wireless communication protocols dedicatedly. In this paper, firstly, we evaluate performance bottlenecks of general multi-core processors with current dominant micro-architecture via typical wireless communication protocol. The results show that the dominant micro-architecture mismatches to demands of wireless communication protocols, which makes dominant general multi-core processor is inefficient when used in this application field. Secondly, we analyze the essential micro-architectural level reasons for the inefficiency in detail. A typical characteristic of wireless communication protocols is there are lots of random memory accesses in a large memory address space, which results in high miss ratio of on-chip cache hierarchies. The frequent on-chip cache misses result in amounts of off-chip memory access operations, which incurs longer memory access latency as a dominant factor to degrade overall performance. Based on the results, we identify key micro-architectural characteristics that meet demands of wireless communication protocols. Finally, we propose a feasible micro-architecture of multi-core processor for C-RAN, called as CRANarch, the performance results show its improved hardware utilization efficiency and power efficiency when used in C-RAN data centers.

INTEGRATION OF CLOUD COMPUTING PLATFORM TO GRID INFRASTRUCTURE

Both grid and cloud are used to organize large scale calculations and data processing on remote computers. Grid which became a basic computing infrastructure for the Large Hadron Collider experiments provides unified technical solutions for sharing and merging distributed heterogeneous computing resources within big collaboration groups. Cloud became popular among data centers and computing service providers because of flexibility, manageability and efficient hardware utilization. Both share common ideology “computing as a service”, so one can expect additional benefits from their integration. The paper describes our approach to the integration. We propose to use cloud within grid sites for acceleration of application deployment and easy support of multiple virtual organizations by grid sites. The cloud in grid approach has been implemented and tested in Ukrainian National Grid, a part of European Grid Infrastructure.

Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform

In this brief, an efficient dual-scan parallel flipping architecture for a lifting-based 2-D discrete wavelet transform is presented. This proposed novel algorithm is based on a flipping technique to implement a modular and hardware-efficient architecture with a very simple control path. In the proposed algorithm, the serial operation of the lifting data flow is optimized using parallel computations of independent paths in advance with pipeline operation to minimize the critical path to one multiplier delay and to achieve 100% hardware utilization efficiency. The proposed architecture is repeatable and only uses five transposition registers. The architecture can be folded to reduce the data path to only six multipliers and eight adders without affecting the critical path. The architecture implemented on a field-programmable gate-array target indicates better hardware efficiency.