Image encoder architecture design using dual scan based DWT with vector quantization

Abstract

Vector quantizer block requires additional hardware resources, it was demonstrated that the codebook generated by coding the residual block makes the image codec more robust. This efficient algorithm is mainly based on flipping technique. First, a three level DWT is performed on the original image resulting in ten separate sub bands. These sub bands are then vector quantized. To implement a hardware efficient and modular architecture with a very simple control path this proposed method is presented. To minimize the critical path to one multiplier delay and to achieve 100% hardware utilization efficiency, the serial operation is optimized using parallel computation in advance with pipeline operation of independent path. This algorithm uses only five transposition register and it is repeatable architecture. Data path can be reduced to six multipliers and eight adders by folding this architecture without affecting the critical path.