Efficient Hardware Platform Research Articles

Advanced computer architecture optimization for machine learning/deep learning

Abstract The recent progress in Machine Learning (Géron, 2022) and particularly Deep Learning (Goodfellow, 2016) models exposed the limitations of traditional computer architectures. Modern algorithms demonstrate highly increased computational demands and data requirements that most existing architectures cannot handle efficiently. These demands result in training speed, inference latency, and power consumption bottlenecks, which is why advanced methods of computer architecture optimization are required to enable the development of ML/DL-dedicated efficient hardware platforms (Engineers, 2019). The optimization of computer architecture for applications of ML/DL becomes critical, due to the tremendous demand for efficient execution of complex computations by Neural Networks (Goodfellow, 2016). This paper reviewed the numerous approaches and methods utilized to optimize computer architecture for ML/DL workloads. The following sections contain substantial discussion concerning the hardware-level optimizations, enhancements of traditional software frameworks and their unique versions, and innovative explorations of architectures. In particular, we discussed hardware including specialized accelerators, which can improve the performance and efficiency of a computation system using various techniques, specifically describing accelerators like CPUs (multicore) (Hennessy, 2017), GPUs (Hwu, 2015) and TPUs (Contributors, 2017), parallelism in multicore architectures, data movement in hardware systems, especially techniques such as caching and sparsity, compression, and quantization, other special techniques and configurations, such as using specialized data formats, and measurement sparsity. Moreover, this paper provided a comprehensive analysis of current trends in software frameworks, Data Movement optimization strategies (A.Bienz, 2021), sparsity, quantization and compression methods, using ML for architecture exploration, and, DVFS (Hennessy, 2017),, which provides strategies for maximizing hardware utilization and power consumption during training, machine learning, dynamic voltage, and frequency scaling, runtime systems. Finally, the paper discussed research opportunity directions and the possibilities of computer architecture optimization influence in various industrial and academic areas of ML/DL technologies. The objective of implementing these optimization techniques is to largely minimize the current gap between the computational needs of ML/DL algorithms and the current hardware’s capability. This will lead to significant improvements in training times, enable real-time inference for various applications, and ultimately unlock the full potential of cutting-edge machine learning algorithms.

LunarSim: Lunar Rover Simulator Focused on High Visual Fidelity and ROS 2 Integration for Advanced Computer Vision Algorithm Development

Autonomous lunar exploration is a complex task that requires the development of sophisticated algorithms to control the movement of lunar rovers in a challenging environment, based on visual feedback. To train and evaluate these algorithms, it is crucial to have access to both a simulation framework and data that accurately represent the conditions on the lunar surface, with the main focus on providing the visual fidelity necessary for computer vision algorithm development. In this paper, we present a lunar-orientated robotic simulation environment, developed using the Unity game engine, built on top of robot operating system 2 (ROS 2), which enables researchers to generate quality synthetic vision data and test their algorithms for autonomous perception and navigation of lunar rovers in a controlled environment. To demonstrate the versatility of the simulator, we present several use cases in which it is deployed on various efficient hardware platforms, including FPGA and Edge AI devices, to evaluate the performance of different vision-based algorithms for lunar exploration. In general, the simulation environment provides a valuable tool for researchers developing lunar rover systems.

Experimental evaluation of digitally verifiable photonic computing for blockchain and cryptocurrency

As blockchain technology and cryptocurrency become increasingly mainstream, photonic computing has emerged as an efficient hardware platform that reduces ever-increasing energy costs required to verify transactions in decentralized cryptonetworks. To reduce sensitivity of these verifications to photonic hardware error, we propose and experimentally demonstrate a cryptographic scheme, LightHash, that implements robust, low-bit precision matrix multiplication in programmable silicon photonic networks. We demonstrate an error mitigation scheme to reduce error by averaging computation across circuits, and simulate energy-efficiency-error trade-offs for large circuit sizes. We conclude that our error-resistant and efficient hardware solution can potentially generate a new market for decentralized photonic blockchain.

Implementation of input correlation learning with an optoelectronic dendritic unit

The implementation of machine learning concepts using optoelectronic and photonic components is rapidly advancing. Here, we use the recently introduced notion of optical dendritic structures, which aspires to transfer neurobiological principles to photonics computation. In real neurons, plasticity—the modification of the connectivity between neurons due to their activity—plays a fundamental role in learning. In the current work, we investigate theoretically and experimentally an artificial dendritic structure that implements a modified Hebbian learning model, called input correlation (ICO) learning. The presented optical fiber-based dendritic structure employs the summation of the different optical intensities propagating along the optical dendritic branches and uses Gigahertz-bandwidth modulation via semiconductor optical amplifiers to apply the necessary plasticity rules. In its full deployment, this optoelectronic ICO learning analog can be an efficient hardware platform for ultra-fast control.

Simulated annealing with surface acoustic wave in a dipole-coupled array of magnetostrictive nanomagnets for collective ground state computing

There is significant current interest in using arrays of interacting nanomagnets as efficient hardware platforms to solve difficult computational problems such as image processing, computer vision or combinatorial optimization. Problem variables are encoded in the magnetization states of the nanomagnets and the array is allowed to relax to the ground state, wherein the magnetic order represents the solution to the problem. This strategy is energy-frugal and ultrafast, since it does not involve software (executing instruction sets), but unfortunately it fails if the system gets stuck in a metastable state from which it cannot escape to the ground state. Here, we demonstrate, in a small system of dipole-coupled 3 × 3 array of magnetostrictive nanomagnets fabricated on a piezoelectric substrate, how the system can be driven out of the metastable state into the ground state with a surface acoustic wave. This process emulates ‘simulated annealing’, which is a well-known algorithm of finding the optimal solution of a function (representing the ground state) by driving the function out of a sub-optimal solution (representing a metastable state) by following a sequence of steps.

Flexible and efficient hardware platform and architectures for waveform design and proof-of-concept in the context of 5G

Several technical contributions are emerging nowadays to fulfill the new requirements foreseen in the 5th generation (5G) of mobile communication systems. Among these contributions, different variants of waveform design are proposed for the new radio air interface as alternative to orthogonal frequency-division multiplexing (OFDM) adopted in 4G. However, in order to prove the feasibility and the benefits of the proposed waveforms, practical hardware implementations are necessary. This paper presents one of the first flexible and efficient hardware platforms for waveform design and proof-of-concept. The proposed platform constitutes a complete hardware/software development environment, with digital processing, radio frequency boards, and all associated interfaces for control, communication, and display. Furthermore, the proposed platform allows the support of several communication scenarios as foreseen in 5G. Promising waveform candidates are implemented, in addition to OFDM, with careful architectural choices to allow fair comparisons. Particularly, this paper presents novel hardware architectures for the UF-OFDM transmitter and receiver.

A Design of the Signal Processing Hardware Platform for Communication Systems

In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900K gates, two DSPs with maximum 8,000 MIPS at 1GHz clock, 2-channel ADC and DAC supporting maximum 125MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16d software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.