Efficient FPGA Implementation Research Articles

Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function.

The implementation of neural networks (NNs) on edge devices enables local processing of wireless data, but faces challenges such as high computational complexity and memory requirements when deep neural networks (DNNs) are used. Shallow neural networks customized for specific problems are more efficient, requiring fewer resources and resulting in a lower latency solution. An additional benefit of the smaller network size is that it is suitable for real-time processing on edge devices. The main concern with shallow neural networks is their accuracy performance compared to DNNs. In this paper, we demonstrate that a customized adaptive activation function (AAF) can meet the accuracy of a DNN. We designed an efficient FPGA implementation for a customized segmented spline curve neural network (SSCNN) structure to replace the traditional fixed activation function with an AAF. We compared our SSCNN with different neural network structures such as a real-valued time-delay neural network (RVTDNN), an augmented real-valued time-delay neural network (ARVTDNN), and deep neural networks with different parameters. Our proposed SSCNN implementation uses 40% fewer hardware resources and no block RAMs compared to the DNN with similar accuracy. We experimentally validated this computationally efficient and memory-saving FPGA implementation of the SSCNN for digital predistortion of radio-frequency (RF) power amplifiers using the AMD/Xilinx RFSoC ZCU111. The implemented solution uses less than 3% of the available resources. The solution also enables an increase of the clock frequency to 221.12 MHz, allowing the transmission of wide bandwidth signals.

Efficient FPGA Implementation of Recursive Least Square Adaptive Filter Using Non- Restoring Division Algorithm

Efficient FPGA Implementation of Recursive Least Square Adaptive Filter Using Non- Restoring Division Algorithm

E$${^2}$$CSM: efficient FPGA implementation of elliptic curve scalar multiplication over generic prime field GF(p)

E$${^2}$$CSM: efficient FPGA implementation of elliptic curve scalar multiplication over generic prime field GF(p)

ИССЛЕДОВАНИЕ КВАНТОВОЙ ВЫЧИСЛИТЕЛЬНОЙ СИСТЕМЫ И РЕАЛИЗАЦИЯ КВАНТОВОГО ЯДРА НА ПЛИС

The quantum core method is one of the most important methods in quantum machine learning.However, the number of features used for quantum nuclei is limited to a few dozen features.The block product state structure is used as a quantum feature map and the implementation ofprogrammable gate matrices is demonstrated. The relevance of these studies lies in the mathematicaland software modeling and implementation of a quantum computing system as part of thedevelopment of the implementation of a quantum core on FPGA for solving classes of problems ofa classical nature. The scientific novelty of this research area is the development of a hybrid simulatorof the quantum cores of a central processing unit (CPU) and a programmable logic integratedcircuit (FPGA) several orders of magnitude faster than a conventional quantum computingsimulator. This joint development of the implemented quantum core and its efficient FPGA implementation allowed numerical simulation of the quantum core based on gates in terms of inputfeatures, up to 780-dimensional features using 4000 samples. We applied the quantum kernel toimage classification problems using the Fashion-MNIST dataset and showed that the quantumkernel is comparable to Gaussian kernels with optimized throughput. The analysis of the work inthis field has shown that a new qualitative level has now been reached, opening up promising opportunitiesfor the implementation of multi-qubit quantum computing. The prospects for implementationand development are connected not only with technological capabilities, but also with solvingthe issues of building effective quantum systems for solving actual mathematical problems,cryptography problems and control (optimization) problems.

A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation

The spectral correlation density (SCD) function is the time-averaged correlation of two spectral components used for analyzing periodic signals with time-varying spectral content. Although the analysis is extremely powerful, it has not been widely adopted in real-time applications due to its high computational complexity. In this article, we present an efficient FPGA implementation of the FFT accumulation method (FAM) for estimating the SCD function and its alpha profile. The implementation uses a linear systolic array with a bi-directional datapath consisting of DSP-based processing elements (PEs) with a dedicated instruction schedule, achieving a PE utilization of 88.2%. The 128-PE implementation achieves a clock frequency in excess of 530 MHz and consumes 151K LUTs, 151K FFs, 264 BRAMs, 4 URAMs, and 1,054 DSPs, which is less than 36% of the logic fabric on a Zynq UltraScale+ XCZU28DR-2FFVG1517E RFSoC device. It has a modest 12.5W power consumption and an energy efficiency of 4,832 MOPS/W, which is 20.6× better than the published state-of-the-art GPU implementation. In terms of throughput, it achieves 15,340 windows/s (15,340 windows/s × 2,048 samples/window = 31.4 MS/s), which is a 4.65× improvement compared to the above-mentioned GPU implementation and 807× compared to an existing hybrid FPGA-GPU implementation.

A highly efficient FPGA implementation of AES for high throughput IoT applications

With nearly 500 billion connected devices in 2025, information security will be the main concern of the researchers. It is the driving force in developing resource efficient cryptographic solutions. In this paper, we present a high throughput AES design with 32-bit data path that achieves the high efficiency via FPGA implementation. With the help of data path compression and effective utilization of FPGA architecture, the resource consumption is minimized. Galois field arithmetic is utilized for s-box implementation. Separate S-box for key generation has been employed to achieve higher throughput and low latency. The proposed design has been synthesized by PlanAhead software and implemented on different Xilinx FPGAs. It is compared with AES implementations. With a throughput of 2.34 Gbps and efficiency of 5.10 Mbps/slice, the design outperforms different lightweight ciphers. High throughput and low latency make it suitable for surveillance applications in IoT and smart grid.

Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing

Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, the Anti-Symmetric Product Coding (APC) and Odd Multiple Storage (OMS) modules are utilized to implement the reconfigurable FIR filter (RFIR–APC–OMS). Herein, the APC–OMS module is used to reduce the area of the RFIR architecture. The performance of the RFIR–APC–OMS is analyzed in terms of: area, power, delay, LUT, flip flop, slices, and frequency. RFIR–APC–OMS has reduced 3.44% of area compared to the existing RFIR architecture employing the Dynamic Reconfigurable Partial Product Generator (DRPPG) module.

FPGA realization of fractals based on a new generalized complex logistic map

This paper introduces a new generalized complex logistic map and the FPGA realization of a corresponding fractal generation application. The chaotic properties of the proposed map are studied through the stability conditions, bifurcation behavior and maximum Lyapunov exponent (MLE). A relation between the mathematical analysis and fractal behavior is demonstrated, which enables formulating the fractal limits. A compact fractal generation process is presented, which results in designing and implementing an optimized hardware architecture. An efficient FPGA implementation of the fractal behavior is validated experimentally on Artix-7 FPGA board. Two examples of fractal implementation are verified, yielding frequencies of 34.593MHz and 31.979MHz and throughputs of 0.415 Gbit/s, 0.384 Gbit/s. Compared to recent related works, the proposed implementation demonstrates its efficient hardware utilization and suitability for potential applications.

Hardware Implementation of Efficient Elliptic Curve Scalar Multiplication using Vedic Multiplier

This paper presents an area efficient and high-speed FPGA implementation of scalar multiplication using a Vedic multiplier. Scalar multiplication is the most important operation in Elliptic Curve Cryptography(ECC), which used for public key generation and the performance of ECC greatly depends on it. The scalar multiplication is multiplying integer k with scalar P to compute Q=kP, where k is private key and P is a base point on the Elliptic curve. The Scalar multiplication underlying finite field arithmetic operation i.e. addition multiplication, squaring and inversion to compute Q. From these finite field operations, multiplication is the most time-consuming operation, occupy more device space and it dominates the speed of Scalar multiplication. This paper presents an efficient implementation of finite field multiplication using a Vedic multiplier. The scalar multiplier is designed over Galois Binary field GF(2233) for field size=233-bit which is secured curve according to NIST. The performances of the proposed design are evaluated by comparing it with Karatsuba based scalar multiplier for area and delay. The results show that the proposed scalar multiplication using Vedic multiplier has consumed 22% less area on FPGA and also has 12% less delay, than Karatsuba, based scalar multiplier. The scalar multiplier is coded in Verilog HDL, synthesize and simulated in Xilinx 13.2 ISE on Virtex6 FPGA.

Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination

Graph cut has been a popular approach widely used to solve the minimum cut problem, which is prevalent in computer vision tasks, although not limited to this field. Push-relabel is considered as one of the promising algorithms of graph cut due to its good potential to be parallelized. However, existing implementations often not only fail to fully exploit the available parallelism but also fail to make full use of the application context to reduce redundant computations. Therefore, they are not competent for application scenarios with high resolution and real-time requirements. To address the issue, we propose three novel techniques to achieve an ultra-fast and efficient FPGA implementation of a push-relabel algorithm. First, we propose a ripple push technique that significantly parallelizes push operations so as to accelerate the push-relabel convergence process. Second, we propose an early-termination technique that effectively removes redundant computations of the push-relabel algorithm. We also theoretically prove the correctness of our early-termination technique. Third, we propose a highly parallelized search technique called flood irrigation search (FIS). It quickly judges early termination conditions based on a pixel parallel architecture. Our implementation focuses on performance-sensitive applications that divide large images into small graph tiles with a specific size. Compared to the state-of-the-art FPGA implementations of push-relabel algorithms, experimental results show that our method can at least achieve <inline-formula> <tex-math notation="LaTeX">$8.93\times $ </tex-math></inline-formula> improvement of execution time.

An efficient FPGA implementation of hand gestures recognition based on neural networks

Different gestures of hand which is a powerful communication channel between man to man and/or man to machine transfers a large amount of information in our daily lives. For example, sign languages are widely used by individuals with speech handicaps. Recognizing hand gestures in the image can be considered a powerful parameter in man-to-machine communication. Although researchers have been trying to implement different hand gestures on several hardware platforms over the past years, their attempts have been confronted by many challenges including restricted resources of hardware platforms, noise factors in the environment, or insufficient accuracy of output in high numbers of experimental samples. In this work, an optimum and parallelized method is developed to implement recognition of different hand gestures in the image on FPGA. The introduced method uses an MLP network with high numbers of hidden layers without wasting resources of the hardware platform. The results comparing the proposed optimized method with the state-of-the-art methods show that the suggested method can be implemented on an FPGA platform with high output accuracy and lower resources.

Fast and efficient FPGA implementation of Polar Codes and SoC test bench

In this paper we describe a novel and efficient System on Chip Field Programmable Gate Array (SoC FPGA) implementation and test bench for short Polar Codes on an Intel DE10-Standard Development Kit. Encoder and decoder are synthesized on the FPGA fabric and the whole functionality of a complete test bench is developed with an embedded ARM-based hard processor system. A Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) parametric design allows synthesis for different code lengths and is suitable for rate-adaptive decoding schemes. We implement fully-unrolled encoder and decoder architectures to achieve high troughputs and lower energy requirements, and achieve an 11% higher throughput than a reference implementation, for short Polar Codes. A novel Merged Processing Element (MPE) is optimized to be used with Sign–Magnitude LLR (SM LLR) discrete representations and pre-computing results in the decoder to reduce latency and resource consumption in comparison to reference designs. A simplified version of this MPE is also implemented, trading higher latencies for lower resource requirements. The SoC test bench design allows single-board automated testing and is also suitable for other error-correcting schemes. Error-correcting performance is evaluated for different combinations of integer and decimal part bits in LLR quantified representations. Also a new simplified non-statistical LLR metric was tested with promising results.

Optimised Floating Point FFT Core for Improved OMP CS System

ABSTRACT The overall network effectiveness in any real time application is defined by the amount of precision used in computing and the capacity to sustain low cost hardware. Within this context optimisation method for floating point computing is starting to emerge gradually due to the enhanced precision level. Particularly with regard to FFT floating point arithmetic model calculation, hardware sophistication is forced to minimise the uncertainty penalty gap between fixed points – FFT floating point prototype. Hardware fusion systems are designed primarily for increasing the use rate of hardware throughout FPU arithmetic calculations. The proposed system to compute mantissa is actually achieved using which hardware counts are reduced in a complex multiplication process and afterwards the signed digit recoding can be reconfigured by a digital integer. Eventually, the technique of radix factorisation is integrated to minimise complex arithmetic associated with phases of FFT. The results show that the algorithm proposed shows decreased field, elevated frequency of operation and an increased level of accuracy. Ultimately, it is contrasted with efficient FPGA implementation that uses the capital and robustness of the proposed fused CSD FP models.

FPGA Realizations of Chaotic Epidemic and Disease Models Including Covid-19

The spread of epidemics and diseases is known to exhibit chaotic dynamics; a fact confirmed by many developed mathematical models. However, to the best of our knowledge, no attempt to realize any of these chaotic models in analog or digital electronic form has been reported in the literature. In this work, we report on the efficient FPGA implementations of three different virus spreading models and one disease progress model. In particular, the Ebola, Influenza, and COVID-19 virus spreading models in addition to a Cancer disease progress model are first numerically analyzed for parameter sensitivity via bifurcation diagrams. Subsequently and despite the large number of parameters and large number of multiplication (or division) operations, these models are efficiently implemented on FPGA platforms using fixed-point architectures. Detailed FPGA design process, hardware architecture and timing analysis are provided for three of the studied models (Ebola, Influenza, and Cancer) on an Altera Cyclone IV EP4CE115F29C7 FPGA chip. All models are also implemented on a high performance Xilinx Artix-7 XC7A100TCSG324 FPGA for comparison of the needed hardware resources. Experimental results showing real-time control of the chaotic dynamics are presented.

Low Error Efficient Approximate Adders for FPGAs

In this paper, we propose a methodology for designing low error efficient approximate adders for FPGAs. The proposed methodology utilizes FPGA resources efficiently to reduce the error of approximate adders. We propose two approximate adders for FPGAs using our methodology: low error and area efficient approximate adder (LEADx), and area and power efficient approximate adder (APEx). Both approximate adders are composed of an accurate and an approximate part. The approximate parts of these adders are designed in a systematic way to minimize the mean square error (MSE). LEADx has lower MSE than the approximate adders in the literature. The 32-bit LEADx with 16-bit approximation has 20% lower MSE than the approximate adder with the lowest MSE in the literature. The 16-bit APEx with 8-bit approximation has the same area, 60% lower MSE, and 4.5% less power consumption in Xilinx Virtex 7 FPGA than the smallest and lowest power consuming approximate adder in the literature. APEx has smaller area and lower power consumption than the other approximate adders in the literature. As a case study, the approximate adders are used in video encoding application. LEADx provided better quality than the other approximate adders for video encoding application. Therefore, our proposed approximate adders can be used for efficient FPGA implementations of error tolerant applications.

Efficient FPGA Implementation of K-Nearest-Neighbor Search Algorithm for 3D LIDAR Localization and Mapping in Smart Vehicles

K-Nearest-Neighbor search (KNN) has been extensively used in the localization and mapping based on 3D laser point clouds in smart vehicles. Considering the real-time requirement of localization and stringent battery constraint in smart vehicles, it is a great challenge to develop highly energy-efficient KNN implementations. Unfortunately, previous KNN implementations either cannot efficiently build search data structures or cannot search efficiently in massive and unevenly distributed point clouds. To solve the issue, we propose a new framework to optimize the implementation of KNN on FPGAs. First, we propose a novel data structure with a spatial subdivision method, which can be built efficiently even for massive point clouds. Second, based on our data structure, we propose a KNN search algorithm which is able to search in unevenly distributed point clouds efficiently. We have implemented the new framework on both FPGA and GPU. Energy efficiency results show that our proposed method is on average 2.1 times and 6.2 times higher than the state-of-the-art implementations of KNN on FPGA and GPU platform, respectively.

Towards Efficient FPGA Implementation of Elliptic Curve Crypto-Processor for Security in IoT and Embedded Devices

An Elliptic Curve Crypto-Processor (ECCP) is a favorite public-key cryptosystem due to its small key size and its high security arithmetic unit. It is applied in constrained devices which often run on batteries and have limited processing, storage capabilities and low power. This research work presents an effective ECCP architecture for security in IoT and embedded devices. A finite field polynomial multiplier takes the most implementation effort of an ECCP because it is the most consuming operation for time and area. So, the objective is to implement the main operation of Point Multiplication (PM) 𝑄=𝑘𝑃 using FPGA. The aim is to obtain the optimal registers number for an area optimization of ECCP architecture. Moreover, it proposes a time optimization of ECCP based on the liveness analysis and exploiting forward paths. Also, a comparison between sequential and parallel hardware design of PM based on Montgomery ladder algorithm is provided.The developed ECCP design is implemented over Galois Fields GF (2163) and GF (2409) on Xilinx Integrated Synthesizes Environment (ISE) Virtex 6 FPGA. In case of GF (2163), this work achieved an area saving that uses 2083 Flip Flops (FFs), 40876 Lookup Tables (LUTs) and 19824 occupied slices. The execution time is 1.963 s runs at a frequency of 369.529 MHz and consumes 5237.00 mW. In case of GF (2409), this work achieved an area saving that uses 8129 Flip Flops (FFs), 42300 Lookup Tables (LUTs) and 18807 occupied slices. The execution time is 29 s runs at a frequency of 253.770 MHz and consumes 2 W. The obtained results are highly comparable with other state-of-the-art crypto-processor designs. The developed ECCP is applied as a case study of a cryptography protocol in ATMs.

Efficient FPGA Implementation of Human Detection from Video Sequences

Detection of Human is a vital and difficult task in computer vision applications like a police investigation, vehicle tracking, and human following. Human detection in video stream is very important in public security management. In such security related cases detecting an object in the video, sequences are very important to understand the behavior of moving objects which normally used in the background subtraction technique. The input data is preprocessed using a modified median filter and Haar transform. The region of interest is extracted using a background subtraction algorithm with remaining spikes removed using threshold technique. The proposed architecture is coded using standard VHDL language and performance is checked in the Spartan-6 FPGA board. The comparison result shows that the proposed architecture is better than the existing method in both hardware and image quality.

VLSI implementation of an efficient MBIST architecture using RLFSR

An area and power efficient FPGA implementation approach of memory built-in self-test (MBIST) is presented in this paper. It is consist of an array of 2-bit linear feedback shift register (LFSR), the switching activity of address generator used in previous MBIST architectures are high. This unwanted switching activity is affecting the power consumption of entire MBIST. We propose the MBIST with ring-based LFSR used to avoid the main problem of power consumption. The 2-bit 2N pattern generator combines with a conventional (N − 2) bit 2(N−2) LFSR and a 2-bit four pattern generator are both controlled separately by a two separate clocks of two different frequencies to generate all possible memory address location of a memory under test. The proposed architecture is implemented on vertex4 FPGA technology in Xilinx software. We showed that results improve the performance of the proposed design by comparing with the existing design.

Efficient implementations of Bloom filter using block RAMs and DSP slices on the FPGA

SummaryThis paper presents efficient FPGA implementations for the Bloom filter, in which a large set P of L‐byte patterns are registered beforehand. Our Bloom filter circuit performs the byte stream pattern test such that it receives an input byte stream t and outputs the bit stream in every clock cycle. Each bit of the output bit stream is 1 if an L‐byte sequence of t starting from the corresponding position is identical with one of the patterns in P. Our circuits use rolling hash functions to compute signatures of all patterns in P registered in Ultra RAMs of the Xilinx UltraScale+ FPGA VU9P. We present two types of implementations, DSP‐based implementation and RAM‐based implementation to compute rolling hash functions of L‐byte sequences using DSP slices and Block RAMs in the FPGA, respectively. The experimental results show that both DSP‐based and RAM‐based Bloom filter circuits for 4800K patterns of length 1024 can perform the byte stream pattern test for 1.1 Gps and 1.3 Gbps input byte streams, respectively, with false positive probability 10−12. Moreover, we can configure DSP‐based and RAM‐based Bloom filter circuits for 100K patterns to work for 54.9 Gbps and 62.2 Gbps input byte streams, respectively, with false positive probability 10−12.