Efficient FPGA Implementation Research Articles

Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.

Efficient FPGA Implementations of Pair and Triplet-Based STDP for Neuromorphic Architectures

Synaptic plasticity is envisioned to bring about learning and memory in the brain. Various plasticity rules have been proposed, among which spike-timing-dependent plasticity (STDP) has gained the highest interest across various neural disciplines, including neuromorphic engineering. Here, we propose highly efficient digital implementations of pair-based STDP (PSTDP) and triplet-based STDP (TSTDP) on field programmable gate arrays that do not require dedicated floating-point multipliers and hence need minimal hardware resources. The implementations are verified by using them to replicate a set of complex experimental data, including those from pair, triplet, quadruplet, frequency-dependent pairing, as well as Bienenstock–Cooper–Munro experiments. We demonstrate that the proposed TSTDP design has a higher operating frequency that leads to $2.46\times $ faster weight adaptation (learning) and achieves 11.55 folds improvement in resource usage, compared to a recent implementation of a calcium-based plasticity rule capable of exhibiting similar learning performance. In addition, we show that the proposed PSTDP and TSTDP designs, respectively, consume $2.38\times $ and $1.78\times $ less resources than the most efficient PSTDP implementation in the literature. As a direct result of the efficiency and powerful synaptic capabilities of the proposed learning modules, they could be integrated into large-scale digital neuromorphic architectures to enable high-performance STDP learning.

Efficient FPGA Implementation of Lightweight Authenticated Encryption and Authenticated Key Distribution Methods for IoT Security

Efficient FPGA Implementation of Lightweight Authenticated Encryption and Authenticated Key Distribution Methods for IoT Security

Partial Least Squares Identification of Multi Look-Up Table Digital Predistorters for Concurrent Dual-Band Envelope Tracking Power Amplifiers

This paper presents a technique to estimate the coefficients of a multiple-look-up table (LUT) digital predistortion (DPD) architecture based on the partial least-squares (PLS) regression method. The proposed 3-D distributed memory LUT architecture is suitable for efficient FPGA implementation and compensates for the distortion arising in concurrent dual-band envelope tracking power amplifiers. On the one hand, a new variant of the orthogonal matching pursuit algorithm is proposed to properly select only the best LUTs of the DPD function in the forward path, and thus reduce the number of required coefficients. On the other hand, the PLS regression method is proposed to address both the regularization problem of the coefficient estimation and, at the same time, reducing the number of coefficients to be estimated in the DPD feedback identification path. Moreover, by exploiting the orthogonality of the PLS transformed matrix, the computational complexity of the parameters’ identification can be significantly simplified. Experimental results will prove how it is possible to reduce the DPD complexity (i.e., the number of coefficients) in both the forward and feedback paths while meeting the targeted linearity levels.

High Speed Area Efficient FPGA Implementation of AES Algorithm

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.

High Speed Area Efficient FPGA Implementation of AES Algorithm

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.

Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA

Convolutional Neural Networks-- (CNNs) based algorithms have been successful in solving image recognition problems, showing very large accuracy improvement. In recent years, deconvolution layers are widely used as key components in the state-of-the-art CNNs for end-to-end training and models to support tasks such as image segmentation and super resolution. However, the deconvolution algorithms are computationally intensive, which limits their applicability to real-time applications. Particularly, there has been little research on the efficient implementations of deconvolution algorithms on FPGA platforms that have been widely used to accelerate CNN algorithms by practitioners and researchers due to their high performance and power efficiency. In this work, we propose and develop deconvolution architecture for efficient FPGA implementation. FPGA-based accelerators are proposed for both deconvolution and CNN algorithms. Besides, memory sharing between the computation modules is proposed for the FPGA-based CNN accelerator as well as for other optimization techniques. A non-linear optimization model based on the performance model is introduced to efficiently explore the design space to achieve optimal processing speed of the system and improve power efficiency. Furthermore, a hardware mapping framework is developed to automatically generate the low-latency hardware design for any given CNN model on the target device. Finally, we implement our designs on Xilinx Zynq ZC706 board and the deconvolution accelerator achieves a performance of 90.1 giga operations per second (GOPS) under 200MHz working frequency and a performance density of 0.10 GOPS/DSP using 32-bit quantization, which significantly outperforms previous designs on FPGAs. A real-time application of scene segmentation on Cityscapes Dataset is used to evaluate our CNN accelerator on Zynq ZC706 board, and the system achieves a performance of 107 GOPS and 0.12 GOPS/DSP using 16-bit quantization and supports up to 17 frames per second for 512 × 512 image inputs with a power consumption of only 9.6W.

Noise estimation for hyperspectral subspace identification on FPGAs

We present a reliable and efficient FPGA implementation of a procedure for the computation of the noise estimation matrix, a key stage for subspace identification of hyperspectral images. Our hardware realization is based on numerically stable orthogonal transformations, avoids the numerical difficulties of the normal equations method for the solution of linear least squares problems (LLS), and exploits the special relations between coupled LLS problems arising in the hyperspectral image. Our modular implementation decomposes the QR factorization that comprises a significant part of the cost into a sequence of suboperations, which can be efficiently computed on an FPGA.

Efficient FPGA Implementation of AES-CCM for IEEE 1609.2 Vehicle Communications Security

Efficient FPGA Implementation of AES-CCM for IEEE 1609.2 Vehicle Communications Security

Efficient ASIC and FPGA implementation of cube architecture

This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. This algorithm converts the cube of a large magnitude number into smaller magnitude number and addition operation. The Vedic sutra for decimal numbers is extended to binary radix-2 number system considering digital platforms. The cubic architecture is synthesised and simulated using Xilinx ISE 14.1 software and implemented on various Field-programmable gate array devices for comparison purpose. The Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of cadence tool is also used considering Application specific integrated circuit platform. The performance parameters such as delay, area and power are obtained from synthesis reports. The results show that the proposed architecture is useful for less area and high-speed application in microprocessor environment.

Efficient FPGA implementation of modular multiplication based on Montgomery algorithm

In order to improve the efficiency of modular multiplication algorithm for FPGA implementation on the prime field modular, an efficient scheme is proposed to accomplish 256×256 bits modular multiplication algorithm. The embedded IP cores of Xilinx FPGA are efficiently utilized to design 512-bit addition and 256×256 bits multiplier. Moreover, the above modules are used to complete Montgomery modular multiplication algorithm. Compared with traditional implementation method, almost 50% running efficiency is improved in our scheme, which has important value to implement complicated cryptographic processor in hardware environment.

Hardware Design of Digital Parametric Conjunctors and t-Norms

This paper presents the hardware design and its implementation on FPGA of several parametric families of digital conjunctors and t-norms built from simple basic t-norms. The authors propose the method of unified presentation of the p-monotone sum, the simplified versions of the ordinal sum of t-norms and t-subnorms, and the method of extension of t-norms by the drastic t-norm. Such unification gives possibility to join several methods of construction of parametric digital conjunctors and t-norms in one scheme with the efficient FPGA implementation. The logic schemes of the proposed design are presented, and the comparative analysis of the latency time and the resources used for the implementation is given.

Реалізація криптографічних алгоритмів на основі ПЛІС для цифрових розподілених систем

This paper presents a single chip efficient FPGA implementation of RSA and DES for Digital Envelope Scheme that targets the Altera Apex 20KE EP20k200EBC356. Implementation of cryptographic algorithms on programmable devices like FPGAs run much faster than on software while preserving physical security of hardware solutions. The high throughput in the implementation of cryptographic algorithms for digital envelope scheme is achieved by means of exploiting the parallelism present in the DES and RSA operations as well as the features of Altera Apex 20KE device family which best suit for system-on-a-programmable-chip (SOPC) applications. The parallelized single chip implementation of DES and RSA for performing the Encryption/Decryption for the Digital envelope scheme offers a throughput of 3.5 Gbits/sec at a system clock rate of 54.7 MHz. This implementation even provides a means for using the DES and RSA separately.

FPGA Implementation of Fir Filter using Distributed Arithmetic Architecture for DWT

This paper presents an efficient FPGA implementation of Finite Impulse Response Filter for Discrete Wavelet Transform using Distributed Arithmetic architecture. This paper proposes a parallel implementation of FIR filter using Distributed Arithmetic Architecture, Distributed Arithmetic Architecture is a multiplier less architecture which uses LookUp Table, ripple carry adder, shift registers. Distributed Arithmetic has an advantaged of less hardware, fast computation time.

Efficient FPGA implementation of a STBC-OFDM combiner for an IEEE 802.16 software radio receiver

In this paper, an efficient FPGA implementation of a 4×4 Space-Time Block Coding (STBC) combiner for MIMO-OFDM software radio receivers is considered. The proposed combiner is based on a low-complexity algorithm which reduces the interference due to the Quasi-Orthogonality of the STBC decoding. In the literature, feedback techniques have been proposed to solve this problem. However, the algorithm introduced in this paper has been conceived in order to avoid the transmission feedback, by estimating the interference factors and removing them. The proposed algorithm exhibits a low computational complexity and complies with the requirements of HW feasibility, considering the execution time/area occupation trade-off.

Efficient parallel architecture for implementation of the CMA adaptive antenna

This paper presents an efficient parallel architecture for implementation of a constant modulus algorithm (CMA) adaptive array antenna. By inserting delay units into the original CMA, a novel delayed CMA (DCMA) that can significantly reduce the associated critical path is derived. Consequently, a pipelining architecture that supports parallel processing is introduced for implementation of the DCMA. In addition to the pipelining technique, a power-of-two multiplier is proposed for the DCMA leading to the efficient FPGA implementation. The effects of delays and finite word-length on the convergence property of CMA are investigated via simulations. Moreover, the synthesized results demonstrate that FPGA implementation of the proposed architecture using power-of-two arithmetic achieves 26.9% resource reduction in comparison with that of fixed-point arithmetic and operating clock frequency higher than 65 MHz. The implemented FPGA was tested to confirm that the designed architecture operates well for CMA.

Code-based cryptography on reconfigurable hardware: tweaking Niederreiter encryption for performance

Today’s public-key schemes that are either based on the factorization or the discrete logarithm problem. Since both problems are closely related, a major breakthrough in cryptanalysis (e.g., with the advent of quantum computing will render nearly all currently employed security system useless. Code-based public-key schemes rely on the alternative security assumption that decoding generic linear binary codes is NP-complete. Two code-based schemes for public-key encryption are available due to McEliece and Niederreiter. Although most researchers analyzed and implemented McEliece’s cryptosystem, we show in this work that the scheme by Niederreiter has some important advantages, such as smaller keys, more practical plain and ciphertext sizes and less computation complexity. In particular, we propose an efficient FPGA implementation of Niederreiter’s scheme that can encrypt more than 1.5 million plaintexts per seconds on a Xilinx Virtex-6 FPGA—outperforming all known implementations of other popular public-key cryptosystems so far.

Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis

Efficient implementation of point multiplication is crucial for elliptic curve cryptographic systems. This paper presents the implementation results of an elliptic curve crypto-processor over binary fields GF(2m) on binary Edwards and generalized Hessian curves using Gaussian normal basis (GNB). We demonstrate how parallelization in higher levels can be performed by full resource utilization of computing point addition and point-doubling formulas for both binary Edwards and generalized Hessian curves. Then, we employ the ω-coordinate differential formulations for computing point multiplication. Using a lookup-table (LUT)-based pipelined and efficient digit-level GNB multiplier, we evaluate the LUT complexity and time-area tradeoffs of the proposed crypto-processor on an FPGA. We also compare the implementation results of point multiplication on these curves with the ones on the traditional binary generic curve. To the best of the authors' knowledge, this is the first FPGA implementation of point multiplication on binary Edwards and generalized Hessian curves represented by ω-coordinates.

FPGA Implementation of MDCT/IMDCT Core in Audio Coding Standards

MDCT is the basic processing component for high quality audio compression. It is also the most computationally intensive operation in layer III of MPEG audio coding standards. In this paper, we have presented an efficient kernel structure and FPGA implementation for forward and inverse MDCT algorithms based on a radix-3 algorithm of a sequence with the length = 3^m. We implemented an efficient MDCT IP core capable of both forward and inverse 36-point MDCT computation. It was found that the computation is faster than the well-known FPGA implementations. The proposed core is suitable for very high performance digital audio compression and Modern mobile applications.

블록 암호 KT-64에 대한 안전성 분석

64-비트 블록 암호 KT-64는 CSPNs (Controlled Substitution-Permutation Networks)를 사용하여 FPGA와 같은 하드웨어 구현에 적합하도록 설계된 블록 암호이다. 본 논문에서는 블록 암호 KT-64의 전체 라운드에 대한 확장된 연관키 부메랑 공격을 제안한다. 본 논문에서 소개하는 공격은 KT-64에 대한 최초의 공격이며, <TEX>$2^{45.5}$</TEX>개의 연관키 선택 평문을 이용하여 <TEX>$2^{65.17}$</TEX>의 KT-64 암호화 연산을 수행하여 KT-64의 비밀키를 복구한다. KT-64 is a 64-bit block cipher which use CSPNs suitable for the efficient FPGA implementation. In this paper, we propose a related-key amplified boomerang attack on the full-round KT-64. The attack on the full-round KT-64 requires <TEX>$2^{45.5}$</TEX> related-key chosen plaintexts and <TEX>$2^{65.17}$</TEX> KT-64 encryptions. This work is the first known cryptanalytic result on KT-64.