Optimised Floating Point FFT Core for Improved OMP CS System

Abstract

ABSTRACT The overall network effectiveness in any real time application is defined by the amount of precision used in computing and the capacity to sustain low cost hardware. Within this context optimisation method for floating point computing is starting to emerge gradually due to the enhanced precision level. Particularly with regard to FFT floating point arithmetic model calculation, hardware sophistication is forced to minimise the uncertainty penalty gap between fixed points – FFT floating point prototype. Hardware fusion systems are designed primarily for increasing the use rate of hardware throughout FPU arithmetic calculations. The proposed system to compute mantissa is actually achieved using which hardware counts are reduced in a complex multiplication process and afterwards the signed digit recoding can be reconfigured by a digital integer. Eventually, the technique of radix factorisation is integrated to minimise complex arithmetic associated with phases of FFT. The results show that the algorithm proposed shows decreased field, elevated frequency of operation and an increased level of accuracy. Ultimately, it is contrasted with efficient FPGA implementation that uses the capital and robustness of the proposed fused CSD FP models.