Efficient Fast Fourier Transform Research Articles

High Speed Area Efficient FFT using Modified SQRT CSLA and 5:3 & 9:4 Compressor

While designing fast fourier transform (FFT) cores, due to the use of multiplexers, memory, or ROMs, there is a substantial increase in power consumption and area. In order to increase speed and throughput, folding and pipelining methods have been approached by various existing designs. But the prime disadvantage of those architectures is the use of multipliers for twiddle multiplications. This present work has proposed fast fourier transform using compressors based multiplier. Both parallel and pipelining techniques have also been used in the proposed designs. Carry Select adder is known to be the fastest adder among the Conventional adder structures. This work uses an efficient Carry select adder by sharing the binary to excess-1 converter (BEC) term. After a logic simplification, we only need one XOR gate, one AND gate and one inverter gate for carry and summation operation. Through the multiplexer, we can select the correct output according to the logic states of the carry in signal. These all design and experiments were carried out on a Xilinx 14.1i Vertex-7 device family.

Design of MOD-R2MDC FFT for MIMO OFDM in wireless telecommunication system

In this paper, an area-efficient low power Fast Fourier Transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless telecommunication system that consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). Orthogonal frequency-division multiplexing is a popular method for high-data-rate wireless transmission. OFDM may be combined with multiple antennas at both the access point and mobile terminal to increase diversity gain and/or enhance system capacity on a time-varying multi path fading channel, resulting in a multiple-input multiple-output OFDM system. This paper describes the VLSI design of an area efficient MOD-R2MDC FFT for MIMO OFDM system targeted to future wireless telecommunication LAN systems. The proposed system is pipeline modified radix 2 multipath delay commutation FFT has been designed for MIMO OFDM. A low-power efficient and full-pipeline architecture enables the real-time application of MIMO OFDM system.

GENESIS: a hybrid-parallel and multi-scale molecular dynamics simulator with enhanced sampling algorithms for biomolecular and cellular simulations.

GENESIS (Generalized-Ensemble Simulation System) is a new software package for molecular dynamics (MD) simulations of macromolecules. It has two MD simulators, called ATDYN and SPDYN. ATDYN is parallelized based on an atomic decomposition algorithm for the simulations of all-atom force-field models as well as coarse-grained Go-like models. SPDYN is highly parallelized based on a domain decomposition scheme, allowing large-scale MD simulations on supercomputers. Hybrid schemes combining OpenMP and MPI are used in both simulators to target modern multicore computer architectures. Key advantages of GENESIS are (1) the highly parallel performance of SPDYN for very large biological systems consisting of more than one million atoms and (2) the availability of various REMD algorithms (T-REMD, REUS, multi-dimensional REMD for both all-atom and Go-like models under the NVT, NPT, NPAT, and NPγT ensembles). The former is achieved by a combination of the midpoint cell method and the efficient three-dimensional Fast Fourier Transform algorithm, where the domain decomposition space is shared in real-space and reciprocal-space calculations. Other features in SPDYN, such as avoiding concurrent memory access, reducing communication times, and usage of parallel input/output files, also contribute to the performance. We show the REMD simulation results of a mixed (POPC/DMPC) lipid bilayer as a real application using GENESIS. GENESIS is released as free software under the GPLv2 licence and can be easily modified for the development of new algorithms and molecular models. WIREs Comput Mol Sci 2015, 5:310–323. doi: 10.1002/wcms.1220

REVISED FAST FOURIER TRANSFORM

The problem of realisation of the Discrete Fourier Transform in on-line is analysed because of non-efficient consuming a time for a newrecalculation of spectrum samples if one discrete-time signal sample or even some small portion of samples in period are replaced by newsample or by new samples, respectively. Using Fast Fourier Transform (FFT) procedure it is assumed that some signal samples in the respective period available for processing digitally are updated by a sensor in real time. It is urgent for every new sample that emerges to have a new spectrum. The ordinary recalculation of spectrum samples even with highly efficient Cooley-Tukey FFT algorithm is not suitable due to speedy varying in time real process to be observed. The idea is that FFT procedure should not be recalculated with every new sample, it is needed just to modify it when the new sample emerges and replaces the old one. We retrieve the recursive formulas for FFT algorithms that refer to the spectrum samples modification. In a case of appearing one new sample, the recursive algorithm calculates a new spectrum samples by simple addition of a residual between an old and new samples, multiplied on respective row of Fourier ‘code’ matrix, to a vector of old spectrum samples. An example of 8-point FFT is presented.

A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation

Fast Fourier transform (FFT) of large number of samples requires huge hardware resources of field programmable gate arrays (FPGA), which needs more area and power. In this paper, we have presented an area efficient architecture of a FFT processor that reuses the butterfly elements several times. The FFT processor is simulated using VHDL and the results are validated on Virtex-6 FPGA. The proposed architecture out performs the conventional architecture of a N-point FFT processor in terms of area which is reduced by a factor of logN 2with negligible increase in processing time.

Multicarrier Spread Spectrum Modulation Schemes and Efficient FFT Algorithms for Cognitive Radio Systems

Spread spectrum (SS) and multicarrier modulation (MCM) techniques are recognized as potential candidates for the design of underlay and interweave cognitive radio (CR) systems, respectively. Direct Sequence Code Division Multiple Access (DS-CDMA) is a spread spectrum technique generally used in underlay CR systems. Orthogonal Frequency Division Multiplexing (OFDM) is the basic MCM technique, primarily used in interweave CR systems. There are other MCM schemes derived from OFDM technique, like Non-Contiguous OFDM, Spread OFDM, and OFDM-OQAM, which are more suitable for CR systems. Multicarrier Spread Spectrum Modulation (MCSSM) schemes like MC-CDMA, MC-DS-CDMA and SS-MC-CDMA, combine DS-CDMA and OFDM techniques in order to improve the CR system performance and adaptability. This article gives a detailed survey of the various spread spectrum and multicarrier modulation schemes proposed in the literature. Fast Fourier Transform (FFT) plays a vital role in all the multicarrier modulation techniques. The FFT part of the modem can be used for spectrum sensing. The performance of the FFT operator plays a crucial role in the overall performance of the system. Since the cognitive radio is an adaptive system, the FFT operator must also be adaptive for various input/output values, in order to save energy and time taken for execution. This article also includes the various efficient FFT algorithms proposed in the literature, which are suitable for CR systems.

Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.

A Collusion-Resistant Fingerprinting System for Restricted Distribution of Digital Documents

Digital fingerprinting is a technique that consists of inserting the ID of an authorized user in the digital content that he requests. This technique has been mainly used to trace back pirate copies of multimedia content such as images, audio, and video. This study proposes the use of state-of-the-art digital fingerprinting techniques in the context of restricted distribution of digital documents. In particular, the system proposed by Kuribayashi for multimedia content is investigated. Extensive simulations show the robustness of the proposed system against average collusion attack. Perceptual transparency of the fingerprinted documents is also studied. Moreover, by using an efficient Fast Fourier Transform core and standard computer machines it is shown that the proposed system is suitable for real-world scenarios.

Collusion-Resistant Audio Fingerprinting System in the Modulated Complex Lapped Transform Domain

Collusion-resistant fingerprinting paradigm seems to be a practical solution to the piracy problem as it allows media owners to detect any unauthorized copy and trace it back to the dishonest users. Despite the billionaire losses in the music industry, most of the collusion-resistant fingerprinting systems are devoted to digital images and very few to audio signals. In this paper, state-of-the-art collusion-resistant fingerprinting ideas are extended to audio signals and the corresponding parameters and operation conditions are proposed. Moreover, in order to carry out fingerprint detection using just a fraction of the pirate audio clip, block-based embedding and its corresponding detector is proposed. Extensive simulations show the robustness of the proposed system against average collusion attack. Moreover, by using an efficient Fast Fourier Transform core and standard computer machines it is shown that the proposed system is suitable for real-world scenarios.

Efficient Computation of the Feedback Filter for the Hybrid Decision Feedback Equalizer in Highly Dispersive Channels

The hybrid decision feedback equalizer (DFE) is a combined time-frequency domain implementation of the conventional time-domain DFE that is able to provide a good trade-off between performance and computational complexity in single carrier transmission over severely frequency-selective channels. In the hybrid DFE the implementation of the feedforward filter is done in the frequency domain, while the feedback filter (FBF) is implemented in the time-domain. The computation of the coefficients for the two filters is usually done in the same domain where they are implemented. A method for frequency-domain computation of the FBF is proposed in the paper. As is known, the key operation in the computation of the FBF is the spectral factorization. In the paper it is proposed to adopt the (cepstral) method for spectral factorization due to Kolmogoroff, which can be efficiently implemented by using the fast Fourier transform (FFT). The application of the method is considered for highly dispersive channels. By using simulations we show that for this type of channels the performance of the proposed method is virtually the same as that obtained by using time-domain approaches. The advantage of the proposed approach is that the efficient FFT gives a substantial reduction of complexity compared to time-domain methods.

Large-scale fast Fourier transform on a heterogeneous multi-core system

As interest in hybrid computing systems increases, people are eager to find new ways to exploit the unique and efficient computational power of the heterogeneous multi-core systems. Although there has been much interest in implementing high-performance fast Fourier transform (FFT) libraries on this kind of system, most existing libraries focus on small-scale FFTs whose data can fit in the local storage of a single accelerator. Real-world FFT applications often require much larger scale FFTs, but it is extremely challenging for heterogeneous multi-core system with distributed architectures to make efficient large FFT implementations. In this paper, we introduce the first known FFT library for the heterogeneous multi-core system with distributed architecture that can solve one-dimensional FFTs larger than what fits in a single accelerator. Our implementation achieves 67% performance improvement of FFTW 3.2.2 (Fastest Fourier Transform in the West) and sustains over 36 single precision FFT GFLOPs ‘end-to-end’ Achieving such high performance requires novel schemes for large-scale FFT factorization, data permutation and all-to-all exchanges, and buffer designs to maximize use of the local storage while minimizing communication overhead. One important finding in this paper is that large-scale FFT on this kind of architecture behaves as data transfer bound which is quite different from other architectures. A significant contribution of this paper is that for each major component of our algorithm, we explore many possible design options and present quantitative performance comparisons. This provides value beyond specific architecture, as it illustrates the fundamental features associated with different communication paradigms and mechanisms for the heterogeneous multi-core system. Today’s computer systems are increasingly being designed to include general purpose accelerators. The techniques in this paper can also be applied to these architectures especially when they have limited local storage or steep cache hierarchies. We also provide insights on applying techniques in this paper to similar architectures.

Icoshift: An effective tool for the alignment of chromatographic data

The Interval Correlation Optimised Shifting algorithm ( icoshift) has recently been introduced for the alignment of nuclear magnetic resonance spectra. The method is based on an insertion/deletion model to shift intervals of spectra/chromatograms and relies on an efficient Fast Fourier Transform based computation core that allows the alignment of large data sets in a few seconds on a standard personal computer. The potential of this programme for the alignment of chromatographic data is outlined with focus on the model used for the correction function. The efficacy of the algorithm is demonstrated on a chromatographic data set with 45 chromatograms of 64,000 data points. Computation time is significantly reduced compared to the Correlation Optimised Warping (COW) algorithm, which is widely used for the alignment of chromatographic signals. Moreover, icoshift proved to perform better than COW in terms of quality of the alignment (viz. of simplicity and peak factor), but without the need for computationally expensive optimisations of the warping meta-parameters required by COW. Principal component analysis (PCA) is used to show how a significant reduction on data complexity was achieved, improving the ability to highlight chemical differences amongst the samples.

Low-cost FFT processor for DVB-T2 applications

An efficient Fast Fourier Transform (FFT) processor is greatly needed for real-time operation in many OFDM applications, such as xDSL, DAB, DVB-T/H, and etc. This paper presents a low-cost Parallel Memory-based FFT (PMB-FFT) processor for DVB-T2 applications. The processor has been designed and implemented in 90nm 1P9M CMOS process. Experimental results show that the PMB-FFT processor meets the DVB-T2 standard with N=32,768 points, and takes only 2.51 mm2 in the core area with a power consumption of 0.89 mW at 25MHz.

A Low-Complexity 128-Point Mixed-Radix FFT Processor for MB-OFDM UWB Systems

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-24 algorithm and a radix-23 algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 µm CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

On-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDM

Problem statement: Fast Fourier Transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence efficient FFT algorithm is always considered. Approach: This study proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 standard for floating-point arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Results: Consequently, synthesis report indicated the latency of 4 clock cycles due to each stage operated within just one clock cycle. The unique structure of designed adder well thought out resulted 6691 equivalent gate count and lead us to obtain low area on chip. Conclusion: The synthesis Xilinx ISE software provided results representing the estimated area and delay for design when it is pipelined to various depths. The report showed the minimum delay of 3.592 ns or maximum frequency of 278.42 MHz.

Efficient MFS algorithms in regular polygonal domains

In this work, we apply the Method of Fundamental Solutions (MFS) to harmonic and biharmonic problems in regular polygonal domains. The matrices resulting from the MFS discretization possess a block circulant structure. This structure is exploited to produce efficient Fast Fourier Transform–based Matrix Decomposition Algorithms for the solution of these problems. The proposed algorithms are tested numerically on several examples.

High-Performance Low-Power FFT Cores

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

The crystallographic fast Fourier transform. Recursive symmetry reduction

Algorithms are presented for maximally efficient computation of the crystallographic fast Fourier transform (FFT). The approach is applicable to all 230 space groups and allows reduction of both the computation time and the memory usage by a factor equal to the number of symmetry operators. The central idea is a recursive reduction of the problem to a series of transforms on grids with no special points. The maximally efficient FFT for such grids has been described in previous papers by the same authors. The interaction between the grid size factorization and the symmetry operators and its influence on the algorithm design are discussed.

An Efficient FFT Processor for DAB Receiver Using Circuit-Sharing Pipeline Design

With the upcoming fourth generation wireless systems and convergence of multiple radio standards into a single terminal, building blocks are needed that can be configured for computing various algorithms used in different standards. Given these trends and requirements, in our previous paper we successfully proposed a circuit-sharing design for the DAB receiver to integrate the FFT (fast Fourier transform) and IMDCT (inverse modified discrete cosine transform) operations into the same functional circuit. The proposed technique reduces hardware overhead, enhances circuit efficiency and significantly reduces the cost of DAB receivers. To further improve the efficiency of our previous work, this investigation proposes another alternative design named the circuit-sharing pipeline design (CSPD) using a single processor with a pipeline scheme to combine two functions, FFT and IMDCT, into the same circuit. The proposed method reduces the required chip area and cost of DAB receivers. Analyzing the existing relationship among IMDCT, DCT (discrete cosine transform) and FFT, the IMDCT function can be replaced using a FFT function. Therefore, it is not necessary to design an extra circuit for IMDCT. The arithmetic unit in the FFT processor can be significantly reduced due to employing the pipeline scheme. Consequently, the circuit redundancies in the IMDCT and FFT functions can be easily eliminated to allow exploitation of the decreased chip area. Results of this study demonstrate that the proposed design can provide advantages such as low gate count and small memory size in the DAB (digital audio broadcasting) receiver.

Non-Gaussian Random Wave Simulation by Two-Dimensional Fourier Transform and Linear Oscillator Response to Morison Force

The one-dimensional fast Fourier transform (FFT) has been applied extensively to simulate Gaussian random wave elevations and water particle kinematics. The actual sea elevations/kinematics exhibit non-Gaussian characteristics that can be represented mathematically by a second-order random wave theory. The elevations/kinematics formulations contain frequency sum and difference terms that usually lead to expensive time-domain dynamic analyses of offshore structural responses. This study aims at a direct and efficient two-dimensional FFT algorithm for simulating the frequency sum terms. For the frequency-difference terms, inverse FFT and forward FFT are implemented, respectively, across the two dimensions of the wave interaction matrix. Given specified wave conditions, the statistics of simulated elevations/kinematics compare well with not only the empirical fits but also the analytical solutions based on a modified eigenvalue/eigenvector approach, while the computational effort of simulation is very economical. In addition, the stochastic analyses in both time domain and frequency domain show that, attributable to the second-order nonlinear wave effects, the near-surface Morison force and induced linear oscillator response are more non-Gaussian than those subjected to Gaussian random waves.