Abstract

In this paper, an area-efficient low power Fast Fourier Transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless telecommunication system that consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). Orthogonal frequency-division multiplexing is a popular method for high-data-rate wireless transmission. OFDM may be combined with multiple antennas at both the access point and mobile terminal to increase diversity gain and/or enhance system capacity on a time-varying multi path fading channel, resulting in a multiple-input multiple-output OFDM system. This paper describes the VLSI design of an area efficient MOD-R2MDC FFT for MIMO OFDM system targeted to future wireless telecommunication LAN systems. The proposed system is pipeline modified radix 2 multipath delay commutation FFT has been designed for MIMO OFDM. A low-power efficient and full-pipeline architecture enables the real-time application of MIMO OFDM system.

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