Design of pipeline R2MDC FFT for implementation of MIMO OFDM transceivers using FPGA

Abstract

In this paper, an area-efficient low power Fast Fourier Transform (FFT) processor is proposed for Multi Input Multi Output--Orthogonal Frequency Division Multiplexing (MIMO-OFDM) that consists of a modified architecture of radix-2 algorithm which is described as Radix-2 multipath delay commutation (R2MDC). Orthogonal frequency-division multiplexing is a popular method for high-data-rate wireless transmission. OFDM may be combined with multiple antennas at both the access point and mobile terminal to increase diversity gain and/or Enhance system capacity on a time-varying multi path fading channel, resulting in a multiple-input multiple-output OFDM system. This paper describes the design of R2MDC FFT for implementation of MIMO OFDM transceiver using FPGA targeted to future wireless LAN systems. The proposed system is pipeline Radix 2multipath delay commutation FFT has been designed for MIMO OFDM. The MIMO OFDM transceivers have been designed according to the proposed OFDM parameters. A low-power efficient and full-pipeline architecture enables the real-time operations of MIMO OFDM transceivers. The FPGA board has been developed to verify their circuit behavior and implementation of MIMO OFDM Transceivers.