Efficient Digital Signal Processor Research Articles

TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization

Accelerators for convolutional neural networks (CNNs) based on field-programmable gate arrays (FPGAs) have drawn much attention in recent years. Two INT-8 multiplications are often implemented on a single digital signal processor (DSP) to improve DSP efficiency and performance. However, most of these works only use DSPs to implement multiplications and do not involve accumulations, which requires a lot of look-up tables (LUTs) and consequently leads to greater energy consumption. Furthermore, these works do not detail how to obtain two signed INT-8 multiplications with a DSP. This brief thus proposes a tiny accelerator for CNNs and a DSP-based processing element (PE) that is designed to implement two signed INT-8 multiply-and-accumulate (MAC) operations to reduce the overhead of LUTs. To allow the DSP to support two signed INT-8 MAC operations and avoid the large loss of accuracy caused by data overflow of partial sums (psum), we apply an efficient DSP optimization approach and a dynamic-precision quantization method. The accelerator is implemented on a Xilinx ZC706 FPGA device and achieves a DSP utilization efficiency <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.7\times $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.3\times $ </tex-math></inline-formula> greater than state-of-the-art accelerators implemented on the same device. Furthermore, our accelerator offers <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.56\times $ </tex-math></inline-formula> greater energy efficiency than other FPGA-based accelerators.

DSP Implementation of a Neural Network Vector Controller for IPM Motor Drives

This paper develops a neural network (NN) vector controller for an interior mounted permanent magnet (IPM) motor by using a Texas Instrument TMS320F28335 digital signal processor (DSP). The NN controller is developed based on the complete state-space equation of an IPM motor and it is trained to achieve optimal control according to approximate dynamic programming (ADP). A DSP-based NN control system is built for an IPM motor drives system, and a high efficient DSP program is developed to implement the NN control algorithm while considering the limited memory and computing capability of the TMS320F28335 DSP. The DSP-based NN controller is able to manage IPM motor control in linear, over, and six-step modulation regions to improve the efficiency of IPM drives and to allow for the full utilization of DC bus voltage with space-vector pulse-width modulation (SVPWM). The experiment results show that the proposed NN controller is able to operate with a sampling period of 0.1ms, even with limited DSP resources of up to 150 MHz cycle time, which is applicable in practical motor industrial implementations. The NN controller has demonstrated a better current and speed tracking performance than the conventional standard vector controller for IPM operation in both the linear and over-modulation regions.

VLSI implementation of residue number system based efficient digital signal processor architecture for wireless sensor nodes

Residue number system (RNS) in computer arithmetic is an efficient parallel computation number system that employs forward conversion, residue arithmetic based arithmetic manipulation and reverses conversion, which all together increases the speed of computation in various digital signal processing applications. Nevertheless power requirement for the wireless sensor node is more important, hence this work focuses on the design and implementation of power efficient RNS based digital signal processor architecture using folded tree based parallel prefix adder by employing Chinese Remainder Theorem—I.

OpenMDSP: Extending OpenMP to Program Multi-Core DSPs

Multi-core digital signal processors (DSPs) are widely used in wireless telecommunication, core network transcoding, industrial control, and audio/video processing technologies, among others. In comparison with general-purpose multi-processors, multi-core DSPs normally have a more complex memory hierarchy, such as on-chip core-local memory and non-cache-coherent shared memory. As a result, efficient multi-core DSP applications are very difficult to write. The current approach used to program multi-core DSPs is based on proprietary vendor software development kits (SDKs), which only provide low-level, non-portable primitives. While it is acceptable to write coarse-grained task-level parallel code with these SDKs, writing fine-grained data parallel code with SDKs is a very tedious and error-prone approach. We believe that it is desirable to possess a high-level and portable parallel programming model for multi-core DSPs. In this paper, we propose OpenMDSP, an extension of OpenMP designed for multi-core DSPs. The goal of OpenMDSP is to fill the gap between the OpenMP memory model and the memory hierarchy of multi-core DSPs. We propose three classes of directives in OpenMDSP, including 1) data placement directives that allow programmers to control the placement of global variables conveniently, 2) distributed array directives that divide a whole array into sections and promote the sections into core-local memory to improve performance, and 3) stream access directives that promote big arrays into core-local memory section by section during parallel loop processing while hiding the latency of data movement by the direct memory access (DMA) of a DSP. We implement the compiler and runtime system for OpenMDSP on FreeScale MSC8156. The benchmarking results show that seven of nine benchmarks achieve a speedup of more than a factor of 5 when using six threads.

A Software Agent for Speech Abiding Systems

Problem statement: In order to bring speech into the mainstream of business process an efficient digital signal processor is necessary. The Fast Fourier Transform (FFT) and the butter fly structure symmetry will enable the harwaring easier. With the DSP and software proposed, togetherly established by means of a system, named here as “Speech Abiding System (SAS)”, a software agent, which involves the digital representation of speech signals and the use of digital processors to analyze, synthesize, or modify such signals. The proposed SAS addresses the issues in two parts. Part I: Capturing the Speaker and the Language independent error free Speech Content for speech applications processing and Part II: To accomplish the speech content as an input to the Speech User Applications/Interface (SUI). Approach: Discrete Fourier Transform (DFT) of the speech signal is the essential ingredient to evolve this SAS and Discrete-Time Fourier Transform (DTFT) links the discrete-time domain to the continuous-frequency domain. The direct computation of DFT is prohibitively expensive in terms of the required computer operations. Fortunately, a number of “fast” transforms have been developed that are mathematically equivalent to the DFT, but which require significantly a fewer computer operations for their implementation. Results: From Part-I, the SAS able to capture an error free Speech content to facilitate the speech as a good input in the main stream of business processing. Part-II provides an environment to implement the speech user applications at a primitive level. Conclusion/Recommendations: The SAS agent along with the required hardware architecture, a Finite State Automata (FSA) machine can be created to develop global oriented domain specific speech user applications easily. It will have a major impact on interoperability and disintermediation in the Information Technology Cycle (ITC) for computer program generating.

Single-phase three-level regular-sampled selective harmonic elimination PWM

A new harmonic elimination PWM strategy for single-phase VSI and CSI inverters is presented which closely approximates the exact switching angles produced offline for the harmonic elimination PWM (HEPWM) strategy. The new strategy is developed using well known regular-sampled techniques which enable the calculation of the switching angles in real-time, allowing a simple and efficient digital signal processor implementation. Experimental and computed results are presented in terms of total harmonic distortion and harmonic performance to highlight the advantages of the strategy and to confirm the theoretical developments.

Modified wave digital filters for improved implementation by commercial digital signal processors

While wave digital filters (WDFs) can always be implemented by commercially available integrated digital signal processors (DSPs), the efficiency of such implementations leaves room for improvement. Modified forms of WDFs are therefore derived that yield much more efficient DSP implementations than those previously available. The approach is particularly suitable for lattice WDFs. The modified WDF structures can be easily built in such a way that they possess all stability properties desired under signal quantization, i.e. not only the absence of small- and large-scale limit cycles, but also, for example, forced-response stability and related properties.