Wave Function Penetration Effects Research Articles

Performance Analysis of InAs/AlSb MOS-HEMT by Self-Consistent Capacitance-Voltage Characterization and Direct Tunneling Gate Leakage Current

In this paper, Capacitance-Voltage (CV) characteristics and direct tunneling gate leakage performance of InAs/AlSb Metal Oxide Semiconductor High Electron Mobility Transistor (MOS-HEMT) are investigated. 1-D coupled Schrӧdinger-Poisson equations are solved for electrostatic characterization of InAs/AlSb MOS-HEMT considering wave function penetration and strain effects. Using modified Wentzel–Kramers–Brillouin (WKB) method for transmission probability, direct tunneling gate leakage current is also calculated for the MOS-HEMT structure. Dependence of CV characteristics and direct tunneling gate leakage current on some important process and physical parameters such as oxide thickness, channel thickness, capping layer composition, gate dielectric material, doping concentration of delta layer and temperature are studied in this work. Our simulation results agree the pattern of variation with the experimental results reported by H. K. Lin et al.

III-V Tri-Gate Quantum-Well Mosfet for 10nm Technology and Beyond

With sub-10nm node technology approaching fast, counteracting short channel effects (SCEs), sub-threshold conduction, reducing transistor off-current and gate leakage current have become aspects of real concern. Integration of III-V semiconductors in multigate device architectures has become a topic of intense research and study for low power logic implementation [1]. Multigate device architectures like FinFETs, GAA FETs provide better control over channel carrier accumulation and improved short channel performance over planar structures. Recently, In0.53GA0.47As Quantum-Well (QW) Tri-Gate MOSFET with bi-layer high-k dielectrics of Al2O3/HfO2 has been reported with channel width and height scaled down to 30nm and 20nm respectively and gate length scaled down to 60nm [2]. In this work, we present a simulation study of inversion Capacitance-Voltage (C-V) and Threshold (VTH) characteristics of a III-V tri-gate device (Fig.1 inset) using self-consistent modeling. The device structure used for modeling in this study incorporates 2nm Al2O3 with In composition kept at 0.7 in the undoped InGaAs QW channel. The In0.52Al0.48As back barrier thickness is kept at 60nm. In this study TiN has been used as the gate metal. In all these studies, temperature is considered to be fixed at 300K. Finite Element Method (FEM) has been used to solve Schrodinger-Poisson equations in a coupled manner applying proper boundary conditions, using COMSOL Multiphysics and MATLAB, taking into account wave function penetration and other quantum mechanical effects. 2D Schrodinger equation is solved using effective mass approximation and open boundary condition to determine electron wave functions and eigen states in the quantum well. Using carrier wave functions in the tri-gate channel, inversion carrier concentration is determined by applying 1D density of states and Fermi-Dirac distribution function. The effect of fixed oxide charges, interface trap charges and oxide border trap charges is not taken into account. The developed simulator is also benchmarked with the simulation results obtained for a III-V GAA nanowire transistor [3]. A quantum definition of threshold voltage for multigate FETs is available in literature [4]. According to this definition, the threshold voltage can be presented as a combination of classical and quantum terms. Here, peak electron concentration npeak(x,y) and average electron concentration navg are used to define threshold voltage of the device. At threshold point, the profile of npeak(x,y)/navg would show a change in slope which results from shift in carrier accumulation as device operation moves from subthreshold to inversion mode [4]. In this study, same definition of threshold voltage has been used. The simulation reveals strong carrier accumulation at the corners of the oxide/semiconductor interface which is expected for multigate device structures (Fig. 1). The simulation also reveals strong subband quantization in the QW channel (Fig. 2). Occupied subbands below the Fermi level contribute to the carrier concentration. As the device dimension is shrunk, volume inversion effect becomes more and more significant and carriers begin to accumulate at the middle portion of the tri-gate channel. This phenomenon leads to an increase in carrier concentration in the middle portion of the QW fin as channel dimension is scaled (Fig. 3). This phenomenon shifts channel formation towards the middle portion of the tri-gate QW fin. Simulation also reveals higher inversion capacitance at lower In composition in the channel which may be attributed to higher density of states effective mass at lower In composition (Fig. 4). Although variation of top gate oxide thickness reveals effect on inversion capacitance, the threshold voltage remains mostly unchanged with top gate oxide thickness. Study of variable channel dimension while keeping WFin=HFin reveals lower carrier accumulation in the device cross section per unit channel length which may lead to lower inversion capacitance with lower channel dimension (Fig. 5). Lowering channel dimension results in stronger quantum confinement and subband splitting which eventually leads to an increase in threshold voltage (Fig. 6). Lowered In composition in the channel also increases threshold voltage of the device (Fig. 6). In this work, a simulation study of a III-V tri-gate quantum well device for 10nm technology and beyond is presented. The outcome of this work would be useful in the implementation of III-V multigate device structures for high speed and low power logic applications.

Capacitance-Voltage Characteristics of Nanowire Trigate MOSFET Considering Wave Function Penetration

Short channel effects on the gate capacitance of nanowire trigate MOS field-effect transistors are studied considering wave function penetration. Capacitance-Voltage (C‑V) measurements are commonly used in studying gate-oxide quality in detail. C‑V test results offer a wealth of device and process information, including bulk and interface charges. Capacitance indicates switching speed of the MOSFET. It is our goal to minimize capacitance as possible as we can in MOSFET. Due to our necessary to compact the Integrated Circuit as possible as we can for getting small electronics devices. Capacitance determines the speed of the IC. Every engineer in this section should know capacitance of his implementing device MOSFET to get exact result from this device. Whenever we deal with 10X10 nm scale or less device of MOSFET. We must concern the effect of wave function penetration into device in this stage classical mechanics fails to describe exact result of the system because electron can move in only one direction (x), in 3 Dimension, it cannot move in other two direction (y, z). i.e. confined in two direction which is not predictable by classical mechanics here quantum mechanics (QM) gives better solution of this problem. Therefore we consider QM in our study. Here we presented how wave function play vital role considering small area of trigate MOSFET. It is the analytical approach of QM and highly recommendation to use QM rather than CM to get accuracy. This result will be helpful for determining capacitance of trigate MOSFET. DOI: http://dx.doi.org/10.11591/ijece.v2i6.1785

Analysis of temperature and wave function penetration effects in nanoscale double-gate MOSFETs

Wave function penetration has significant impact on nanoscale devices having ultrathin gate oxide. Although wave function penetration effects on ballistic drain current and capacitance-voltage characteristics in nanoscale devices have been reported in literature, to the best of the authors’ knowledge, effects of temperature on drain current incorporating with and without wave function penetration are yet to be studied. In this work, the impacts of temperature, gate dielectric and film thickness in wave function penetration on ballistic drain current of nanoscale double-gate (DG) MOSFETs are presented. The effects are observed using two-dimensional self-consistent solution of Schrödinger and Poisson equations. It has been obtained that temperature effect on drain current is greatly dependent on silicon surface orientation. Drain current of DG MOSFETs fabricated on $$\langle110\rangle$$ surface is more sensitive to temperature compared to $$\langle001\rangle$$ surface. This has been obtained for both the cases with and without incorporating wave function penetration in silicon–gate oxide interface. Electrostatics behind this phenomenon has been explained from the transmission probability of electrons from source to drain which is largely influenced by temperature on $$\langle110\rangle$$ surface compared to $$\langle001\rangle.$$ Moreover, the transmission coefficient is significantly affected by wave function penetration in $$\langle110\rangle \hbox{ than }\langle001\rangle$$ surface. Both these demonstrate greater sensitivity of temperature and wave function penetration in $$\langle110\rangle$$ silicon surface orientation compared to $$\langle001\rangle.$$ Furthermore, gate dielectric with lower conduction band offset and device scaling with thin channel thickness tend to exhibit greater impact of wave function penetration.

Capacitance Compact Model for Ultrathin Low-Electron-Effective-Mass Materials

We present a compact model to calculate the capacitance of undoped high-mobility low-density-of-states materials in double-gate device architecture. Analytical equations for estimating the subband energies, while taking the effect of wavefunction penetration into the gate oxide and the effective mass discontinuity, are presented for the first time in a compact modeling framework. The surface potential equation for a two subband system is solved, assuming Fermi-Dirac statistics, and compared to numerical Schrodinger-Poisson simulations. The importance of accurately treating the charge profile distribution is illustrated, and an analytical expression for the effective oxide thickness to model the charge centroid is developed.

A physically based, accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal-oxide-semiconductor field-effect transistors

We present a physically based, accurate model of the direct tunneling gate current of nanoscale metal-oxide-semiconductor field-effect transistors considering quantum mechanical effects. Effect of wave function penetration into the gate dielectric is also incorporated. When electrons tunnel from the metal oxide semiconductor inversion layer to the gate, the eigenenergies of the quasi-bound states turn out to be complex quantities. The imaginary part of these complex eigenenergies, Γij, are required to estimate the finite lifetimes of these states. We present an empirical equation of Γij as a function of surface potential. Inversion layer electron concentration is determined using eigenenergies, calculated by modified Airy function approximation. Hence, a compact model of direct tunneling gate current is proposed using a novel approach. Good agreement of the proposed compact model with self-consistent numerical simulator and published experimental data for a wide range of substrate doping densities and oxide thicknesses states the accuracy and robustness of the proposed model. The proposed model can well be extended for devices with high-κ/stack gate dielectrics introducing necessary modifications. Copyright © 2011 John Wiley & Sons, Ltd.

A self-consistent algorithm to extract interface trap states of MOS devices on alternative high-mobility substrates

A new self-consistent technique is proposed to simultaneously extract the density of interface traps (Dit) and flat-band voltages of MOS structures fabricated on technologically relevant high-mobility semiconductors with arbitrary combination of gate stacks. The technique is based on novel analysis of the low-frequency C–V measurement. The two major problems associated with the existing low-frequency C–V technique for arbitrary substrate/oxide combinations are resolved by (i) accurate calculation of the ideal semiconductor capacitance using a self-consistent, quantum–mechanical model including wave function penetration effect, and (ii) accurate determination of the flat-band voltage utilizing an iterative scheme. The proposed technique has been applied to extract Dit profiles of a number of MOS structures fabricated on III–V semiconductors like InGaAs (with ALD grown Al2O3 gate dielectric) and elemental semiconductors like Ge (with GeON gate dielectric). The advantages of the proposed technique have been demonstrated by comparing with Dit profiles extracted from other capacitor-based extraction methods.

A Physically Based Accurate Model for Quantum Mechanical Correction to the Surface Potential of Nanoscale MOSFETs

We present a physically based explicit analytical model for the quantum mechanical (QM) correction to the surface potential of nanoscale metal-oxide-semiconductor (MOS) devices. The effect of wave function penetration into the gate dielectric is taken into account. Instead of using the band-gap widening approach, which indirectly includes QM correction, the proposed correction term is directly added to the semiclassical surface potential. Under accumulation bias, charges in extended states and quantized states contribute to the surface potential in different ways. The proposed QM correction considers this difference in contributions. Comparison with two existing analytical QM correction models and two self-consistent QM numerical models show that the proposed correction is more accurate than the existing analytical models. The improvement achieved under the accumulation bias is particularly significant. The gate C-V characteristics of a number of different MOS devices have been simulated using the proposed correction. Excellent agreement with published experimental data has been observed.

Wave function penetration effects in double gate metal-oxide-semiconductor field-effect-transistors: impact on ballistic drain current with device scaling

A study of the evolution of wave function penetration effects on ballistic drain current (ID) in nanoscale double gate (DG) metal-oxide-semiconductor field-effect-transistors (MOSFET) with the downscaling of device dimensions is presented. The electrostatics of the devices is calculated through the self-consistent solution of two dimensional Schrödinger and Poisson equations. HfO2/SiO2 stack is considered as the gate-dielectric material. It is observed that wave function penetration increases drain current in DG MOSFETs fabricated on (110) silicon, and the off-state current is more sensitive to the penetration effects than the on-state current. Numerical results show that the magnitude of the relative increase in ID due to wave function penetration increases sharply with the downscaling of silicon body thickness. On the other hand, the impact of the downscaling of gate length on the penetration effects depends on the gate bias. The relative increase in the off-state current due to wave function penetration decreases with the scaling of the gate length, while the variation in the relative increase in the on-state current with the gate length is insignificant. Drain-induced barrier lowering plays an important role in determining the effects of wave function penetration on the ballistic drain current with device scaling. Wave function penetration effect decreases the threshold voltage and increases the on-state transconductance. This phenomena becomes stronger with the scaling of the silicon body thickness. However, gate length scaling has little influence on these parameters. With the simultaneous scaling of the body thickness and the gate length, wave function penetration effects on all the parameters become more dominant. Physical explanation for these observations are provided.

Wave function penetration effects on ballistic drain current in double gate MOSFETs fabricated on (1 0 0) and (1 1 0) silicon surfaces

A comparison of wave function penetration effects on ballistic drain current ( I D ) in nanoscale double gate (DG) MOSFETs fabricated on (1 0 0) and (1 1 0) silicon surfaces is presented. MOS electrostatics is determined from the self consistent solution of 2D Schrödinger and Poisson equations and I D is calculated assuming that the ballistic transport through each subband is independent. Numerical results show that I D is much more sensitive to wave function penetration in (1 1 0) DG MOSFETs than in (1 0 0) DG MOSFETs. This difference is due to the much heavier quantization effective mass in the longitudinal valley of (1 0 0) silicon relative to that in the fourfold valley (Δ 4) of (1 1 0) silicon. It is also observed that in (1 0 0) devices, penetration effect is not sensitive to device scaling, whereas in (1 1 0) devices, penetration effect increases significantly with device scaling. The wave function penetration effect on I D may be represented in terms of a reduction of the threshold voltage.

An Improved Model for Calculating Tunneling Current in Nanocrystal Memory

A methodology to compute tunneling currents in a nanocrystal (NC) memory cell is presented to reveal the positive impact of using metal NCs as storage nodes. An analytical model for quantifying the NC effect on electrostatic potential has been used with a transmission line analogy-based quantum mechanical method to calculate the tunneling current. The model includes the effects of the electron wave function penetration into the gate dielectric and also shows the influence of NCs' spacing and material properties on the programming characteristic of the memory cell. Results can be used in optimizing the structure for maximum programming efficiency.

Modeling of charge quantization and wave function penetration effects in a metal–oxide–semiconductor system with ultrathin gate oxide

We investigated the charge quantization and wave function penetration effects in a metal–oxide–semiconductor structure using an in-house developed quantum mechanical (QM) capacitance–voltage (C–V) simulator (denoted as NUSQM), which solves the Schrödinger and Poisson equations self-consistently. The C–V results obtained from the NUSQM simulator were compared with those obtained from other QM simulators in the literature (i.e., U.C. Berkeley, U.T. Quant, NEMO, and North Carolina State University). The results in the present work are generally in good agreement with the other simulators in the inversion region while some discrepancies exist among the different simulators in the accumulation region. It was found that the wave function penetration has a non-negligible effect on the gate capacitance and resulting C–V curves when the oxide thickness decreases to 1 nm and below.

Wave function penetration effects on current–voltage characteristics of ballistic metal–oxide–semiconductor transistors

Effects of wave function penetration into the gate oxide on the drain current in ballistic metal–oxide–semiconductor field-effect transistors (MOSFETs) are studied. MOS electrostatics is treated by self-consistent solution of one-dimensional Schrödinger and Poisson equations. Schrödinger equation is solved with an open boundary condition applied at the silicon–gate-oxide interface. Two-dimensional effects and inelastic scattering of carriers are neglected in the drain current calculation. Numerical results show that wave function penetration has nontrivial effects on modeling of the drain current. These effects are found to depend on the silicon surface orientation. In devices fabricated on (100) silicon, drain current and transconductance decrease when penetration effects are considered although the gate capacitance increases in the presence of penetration. On the other hand, in devices on (111) silicon, penetration effects increase the drain current and transconductance. An explanation for the opposite dependence of the penetration effects on surface orientation is provided. It also appears that the use of only the lowest subband to describe MOS electrostatics, as done in some studies, will lead to significant error in the calculation of drain currents.

A comparison of wave-function penetration effects on gate capacitance in deep submicron n- and p-MOSFETs

We have calculated the effects of wave function penetration into the gate-oxide on the modeling of gate capacitance in deep submicron p-MOSFETs on [100] silicon for the first time. These results are compared to those of n-MOSFETs. Self-consistent calculations show that contrary to the common belief, penetration effects are more pronounced in p-MOS devices. The error in inversion capacitance due to neglect of penetration effects has opposite dependence on substrate doping density for n-MOS and p-MOS structures. Consequently, the error in gate capacitance for an n-MOSFET in strong inversion is strongly dependent on doping density, while that for a p-MOSFET essentially does not depend on doping density. An explanation for this unusual result is also provided. Although the error in gate capacitance is only a few percent, it will have nontrivial effects on device parameter extraction from capacitance-voltage (C-V) measurements.

Effects of inelastic scattering on direct tunneling gate leakage current in deep submicron metal–oxide–semiconductor transistors

Direct tunneling gate leakage current in metal–oxide–semiconductor (MOS) structures with ultrathin gate oxides is studied. The effects of inelastic scattering of inversion carriers in the gate-oxide region is taken into account in the current calculation. Open boundary conditions, incorporating the effects of wave function penetration into the gate oxide, are used to solve Schrödinger’s equation. The proposed technique, based on the Green’s function formalism, is numerically efficient and does not require determination of complex eigenenergies of a non-Hermitian matrix. Self-consistent calculations for n-type MOS devices are compared with experimental results. Excellent agreement between simulated and measured data is obtained when appropriate spatial and gate bias dependence of the inelastic scattering rate is taken into account. It is shown that due to inelastic scattering, at low gate voltages, the gate current increases significantly in devices with oxide thickness equal to 2 nm or higher. However, when the oxide thickness is reduced below 2 nm, inelastic scattering has no significant effect on gate current. The existing mismatch at lower gate voltages between experimental and modeled direct tunneling currents in devices with gate-oxide width equal to or greater than 2 nm is explained in terms of inelastic scattering effects.

Effects of wave function penetration into the gate-oxide on self-consistent modeling of scaled MOSFETs

Effects of wave function penetration into gate-oxide on properties of scaled nMOS devices in deep submicron regime are studied, taking into account the penetration effects on the solutions of both Schrodinger's and Poisson's equations. Numerical results show that penetration effects on properties of inversion layers become more important with scaling down of device dimensions. These effects are also more pronounced at strong inversion.

Understanding the effects of wave function penetration on the inversion layer capacitance of NMOSFETs

A comprehensive analysis of the effects of wave function penetration on the capacitance of NMOS capacitors has been performed for the first time, using a self-consistent Schrodinger-Poisson solver. The study reveals that accounting for wave function penetration into the gate dielectric causes carrier profile to be shifted closer to the gate dielectric reducing the electrical oxide thickness. This shift increases with increasing gate voltage. For example, in one simulation, the peak is shifted by about 0.2 nm at a surface field of 1.96 MV/cm and 0.33 nm at a surface field of 3.7 MV/cm. This shifting results in all increased capacitance. The increase in capacitance observed in the inversion region is relatively insignificant when a poly gate electrode with a doping of less than 1/spl times/10/sup 20/ cm/sup -3/ is used due to the poly-depletion effect. A physical picture of the effect of physical thickness on the tunneling current is also presented.

Alloy scattering-limited mobility in narrow quantum wells

Alloy scattering-limited mobility is calculated for narrow quantum wells of GaAs/Ga0.7Al0.3As, Ga0.47In0.5As/InP, and Al0.48In0.5As/Ga0.47In0.53As systems with widths down to 0.5 nm, taking into account the energy-band nonparabolicity and the effects of wave-function penetration into the barrier layer. Values of mobility are found to be significantly different from those given by the formulas derived earlier for wide wells.