Effects Of Soft Errors Research Articles

A characterization of soft-error sensitivity in data-parallel and model-parallel distributed deep learning

The latest advances in artificial intelligence deep learning models are unprecedented. A wide spectrum of application areas is now thriving thanks to available massive training datasets and gigantic complex neural network models. Those two characteristics demand outstanding computing power that only advanced computing platforms can provide. Therefore, distributed deep learning has become a necessity in capitalizing on the potential of cutting-edge artificial intelligence. Two basic schemes have emerged in distributed learning. First, the data-parallel approach, which aims at dividing the training dataset into multiple computing nodes. Second, the model-parallel approach, which splits layers of a model into several computing nodes. Each scheme has its upsides and downsides, particularly when running on large machines that are susceptible to soft errors. Those errors occur as a consequence of several factors involved in the manufacturing process of current electronic components of supercomputers. On many occasions, those errors are expressed as bit flips that do not cause the whole system to crash, but generate wrong numerical results in computations. To study the effect of soft error on different approaches for distributed learning, we leverage checkpoint alteration, a technique that injects bit flips on checkpoint files. It allows researchers to understand the effect of soft errors on applications that produce checkpoint files in HDF5 format. This paper uses the popular deep learning PyTorch tool on two distributed-learning platforms: one for data-parallel training and one for model-parallel training. We use well-known deep learning models with popular training datasets to provide a picture of how soft errors challenge the training phase of a deep learning model.

Learning-Based Mitigation of Soft Error Effects on Quaternion Kalman Filter Processing

Learning-Based Mitigation of Soft Error Effects on Quaternion Kalman Filter Processing

Investigation of edge computing hardware architectures processing tiny machine learning under neutron-induced radiation effects

This article investigates 14-MeV neutron radiation soft-error effects on two contrasting hardware architectures for edge computing systems, one based on an 8-bit processor and another on a 64-bit processor, both processing three frequently used types of tiny machine learning (ML) algorithms. Experimental results of 14-MeV neutron radiation tests in the different case-study ML algorithms running on the 64-bit processor show that the artificial neural network version using floating point failed more than the other versions, although most failure situations caused no misclassification in the ML inference. Furthermore, considering tiny ML applications demanding the investigated 8-bit and 64-bit computing systems for the same amount of ML inferences, the overall results suggest a preliminary trend that both case-study systems would have similar tolerance to 14-MeV neutron radiation soft errors.

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell.

Soft Error Effects on Arm Microprocessors: Early Estimations versus Chip Measurements

Extensive research efforts are being carried out to evaluate and improve the reliability of computing devices either through beam experiments or simulation-based fault injection. Unfortunately, it is still largely unclear to which extend fault injection can provide an accurate error rate estimation at early stages and if beam experiments can be used to identify the weakest resources in a device. The importance and challenges associated with a timely, but yet realistic reliability evaluation grow with the increase of complexity in both the hardware domain, with the integration of different types of cores in an SoC (System-on-Chip), and the software domain, with the OS (operating system) required to take full advantage of the available resources. In this paper, we combine and analyze data gathered with extensive beam experiments (on the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">final</i> physical CPU hardware) and microarchitectural fault injections (on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">early</i> microarchitectural CPU models). We target a standalone Arm Cortex-A5 CPU and an Arm Cortex-A9 CPU integrated into an SoC and evaluate their reliability in bare-metal and Linux-based configurations. Combining experimental data that covers more than 18 million years of device time with the result of more than 176,000 injections we find that both the SoC integration and the presence of the OS increase the system DUEs (Detected Unrecoverable Errors) rate (for different reasons) but do not significantly impact the SDCs (Silent Data Corruptions) rate which is solely attributed to the CPU core. Our reliability analysis demonstrates that even considering SoC integration and OS inclusion, early, pre-silicon microarchitecture-level fault injection delivers accurate SDC rates estimations and lower bounds for the DUE rates.

Emulating the Effects of Radiation-Induced Soft-Errors for the Reliability Assessment of Neural Networks

Convolutional Neural Networks (CNNs) are currently one of the most widely used predictive models in machine learning. Recent studies have demonstrated that hardware faults induced by radiation fields, including cosmic rays, may significantly impact the CNN inference leading to wrong predictions. Therefore, ensuring the reliability of CNNs is crucial, especially for safety-critical systems. In the literature, several works propose reliability assessments of CNNs mainly based on statistically injected faults. This work presents a software emulator capable of injecting real faults retrieved from radiation tests. Specifically, from the device characterisation of a DRAM memory, we extracted event rates and fault models. The software emulator can reproduce their incidence and access their effect on CNN applications with a reliability assessment precision close to the physical one. Radiation-based physical injections and emulator-based injections are performed on three CNNs (LeNet-5) exploiting different data representations. Their outcomes are compared, and the software results evidence that the emulator is able to reproduce the faulty behaviours observed during the radiation tests for the targeted CNNs. This approach leads to a more concise use of radiation experiments since the extracted fault models can be reused to explore different scenarios (e.g., impact on a different application).

Impact of negative bias temperature instability on single event transients in scaled logic circuits

AbstractAltering the performance of single transistors and integrated circuits at nominal operating conditions over time, as well as soft errors, are serious reliability issues for integrated CMOS circuits, especially when used in space applications. In principle, the effect of soft errors becomes even more critical if the circuit performance degrades over time. To address this detrimental behavior, the impact of performance degradation due to NBTI on the soft error susceptibility of integrated circuits is analyzed thoroughly. For this, we analyze the critical charge sensitivity of the two‐input NAND gate and NOR gate for different operating temperatures at stress times up to 3 years. The results show that the critical charge decreases with the temperature and strongly depends on the input states. Next, we validate the results employing the c17 ISCAS'85 benchmark suite, employing the PTM model with the HSPICE to estimate the soft error at the sensitive nodes. The critical charge is observed to be sensitive to the selected supply voltage and device temperature and thus provides a good measure for the soft error susceptibility with respect to NBTI at various operation conditions.

Soft Error Tolerant Count Min Sketches

The estimation of the frequency of the elements on a set is needed in a wide range of computing applications. For example, to estimate the number of hits that a video gets or the number of packets in a network flow. In some cases, the number of elements in the set is very large and it is not practical to maintain a table with the exact count for each of them. Instead, simpler and more efficient data structures, commonly referred to as sketches, that provide an estimate are used. Among those structures the Count Min Sketch (CMS) is one of the most popular sketches. The CMS provides estimates that have one sided errors. In more detail, the CMS returns an estimate that is equal to or larger than the actual value. An update or check requires a small and constant number of memory accesses and the memory footprint is fixed and does not depend on the number of elements. The CMS relies on several arrays of counters that are stored in memory. Memories are prone to suffer soft errors that flip the contents of memory cells due for example to ionizing radiation. Therefore, it is of interest to study the impact that soft errors can have on the CMS estimates and to propose protection techniques that minimize their effect while requiring low overhead in terms of additional memory and circuitry. To the best of our knowledge this has not been done before. In this article, first the effect of soft errors on the CMS is evaluated by injecting errors. Then, in the second part a protection technique that does not require additional memory bits is presented and compared with the protection using a parity bit. In the last part of the article, the technique is extended to protect also against double adjacent bit errors.

A comprehensive analysis on the resilience of adiabatic logic families against transient faults

With the emergence of various battery operated technologies in different computing domains and the challenge of heating in such technologies, the issue of energy dissipation has become more critical than ever before. In such systems, energy constraints in one hand, and heat generation, on the other hand, necessitates the employment of energy efficient technologies in the fabrication of digital circuits. One possible solution for mitigating the energy dissipation in digital circuits is the use of adiabatic families in the process of designing computing devices. Adiabatic circuits are designed mainly based on the principles of thermodynamics and provide a paradigm shift in the design of digital systems. Nevertheless, their impact on the reliability of digital circuits due to susceptibility to soft errors has not been explored comprehensively. In this paper, we first try to survey some existing adiabatic logic families. Then we attempt to evaluate their reliability by validating their functionality under the effect of soft errors. Our evaluations which were conducted on a set of SPICE simulations have shown that amongst SCRL, 2LAL, RERL, PFAL, 2N2N2P and ECRL families the ECRL family is able to tolerate more than 90% of the injected transient faults and the applications with a high demand of reliability can use this family of adiabatic circuits. Furthermore, we will propose some suggestions for establishing reliable computations through adiabatic circuits.

The Effects of Soft Errors and Mitigation Strategies for Virtualization Servers

Virtualized servers compose the majority of cloud computing environments, where these nodes are used to host multiple clients over the same hardware. Many organizations run online applications by hiring elastic computing resources in order to match demand while reducing fixed costs. However, such organizations are unlikely to take advantage of these benefits for critical applications, as it would expose them to several risks. Among other threats, soft errors are a concern in large-scale reliable servers and are expected to become more frequent as a consequence of smaller transistors and lower operating voltages of integrated circuits. This article characterizes virtualized servers of cloud environments in presence of soft errors. Using fault injection, we collect experimental data to determine the failure modes of applications, operating systems, VMs, and hypervisor. The analysis exposes distinct failure modes, ranging from crash failures of a single virtual machine to silent data corruption in permanent storage. The most frequent failure mode, observed in 10–30 percent of injected errors, consists of a hang affecting multiple virtual machines. Given that such failures are a primary cause of downtime, we develop and evaluate a recovery mechanism which uses online testing and recovers a server from all hangs by rebooting its hypervisor.

Reliable and high performance asymmetric FinFET SRAM cell using back-gate control

As the technology scales down, the performance characteristics are degraded and the reliability of digital circuits against soft error and aging effects are reduced. In this paper, we propose a reliable asymmetric FinFET 6T SRAM cell formed by the combination of tied-gate and independent-gate transistors. In the proposed design, we used a fixed value for the back gate voltages and utilized the back gate control method along with the built-in feedback. HSPICE simulations in 32 nm FinFET technology at VDD = 0.9 V indicate that the proposed cell has the highest read SNM, read speed, write stability, and the least read power consumption amongst recently reported cells. Furthermore, our proposed SRAM structure is the best soft error resilient design and, with a low difference, has the second least hold and read stability degradations against aging effect induced by negative bias temperature instability in comparison with other SRAM cells considered in this paper. In addition, the results demonstrate the efficiency of our proposed cell against process and environmental variations.

32-Bit One Instruction Core: A Low-Cost, Reliable, and Fault-Tolerant Core for Multicore Systems

Abstract Occurrences of both transient and permanent errors pose a major challenge in the wake of burgeoning growth in transistor density. Manufacturing defects and process variants lead to permanent faults, thereby lowering processor yields. In the arithmetic logic unit, single permanent faults result in the absolute failure of processors. Both low-energy neutrons and alpha particles from the cosmos induce transient errors by altering the state of the transistor. In wake of the implications, we postulate a new, reliable, fault-tolerant, low-cost 32-bit one instruction core (OIC) for a multicore system. “Low cost” here means low power and lower area. Notably, 32-bit OIC provides fault-free execution with triple redundant subtractors with one additional subtractor. It only executes one instruction called subleq repetitively in order to emulate the faulty instructions migrated into it by other cores. Hardware synthesis is undertaken to estimate leakage power, dynamic power, critical path delay, and area. The low-power 32-bit OIC consumes 1.3 mW, with a die area of 8,122 μm2. Apart from also adding performance overhead, 32-bit OIC outperforms its competitors with regard to reliability, area, power, and critical path delay. Additionally, the probabilistic estimate with link vulnerability factor—as a new parameter—is introduced to assess the effect of soft errors or transient faults on interconnect wires, which are then quantitatively analyzed to illuminate the resilience of 32-bit OIC hardware structure. Additionally, we propose new design alternatives (including existing ones) for heterogeneous multicore systems in order to develop low-cost solutions with a primary focus on reliability.

An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs

The use of microprocessors in space missions implies that they should be protected against the effects of cosmic radiation. Commonly this objective has been achieved by applying modular redundancy techniques which provide good results in terms of reliability but increase significantly the number of used resources. Because of that, new protection techniques have appeared, trying to establish a trade-off between reliability and resource utilization. In this paper, we propose an application-based methodology, to protect a soft processor implemented in an SRAM-based FPGA, against the effect of soft errors. This is done creating a library of adaptive protection configurations, based on the profiling of the application. This hardware configuration library, combined with the reprogramming capabilities of the FPGA, helps to create an adaptive protection for each application. We propose two partial TMR configurations for the Arithmetic Logic Unit (ALU) as an example of this methodology. The proposed scheme has been tested in a RISC-V soft processor. A fault injection campaign has been performed to test its reliability.

Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows

Formal techniques for the functional verification of System-on-Chip (SoC) hardware have matured significantly over the last years. They can penetrate deeply into a design to exhibit complex functional dependencies between various design components in terms of detailed logical and temporal relationships. They can also provide a well-defined formal relationship between an abstract system model of a design and its concrete implementation at the register-transfer level (RTL). This paper shows how such knowledge available from formal verification can be “condensed” into a database that stores all registers and flip-flops, at which time points they are actually relevant for the correct behavior of the design and when they are not. We show that the comprehensive information on temporary unobservabilities in the design can be of great value to reach two nonfunctional design goals that play a dominant role in many design flows: safety and low power consumption. This paper presents techniques to assess the effects of soft errors by single-event upsets (SEUs) with formal precision and to relate the results of the proposed analysis to an abstract system model. For example, our analysis can determine which soft errors may lead to a system “crash” and which are guaranteed not to cause any harm. For the application of the proposed approach in power optimization, this paper presents techniques for clock gating and power gating. For the examined designs, we observe a reduction of power consumption between 10% and 50% on top of the state-of-the-art commercial power synthesis.

Effect of Soft Errors in Iterative Learning Control and Compensation using Cross-layer Approach

In this paper, we study the effects of radiation-induced soft errors in iterative learning control(ILC) and present the compensation techniques to make the ILC systems robust against soft errors. Soft errors are transient faults, which occur temporarily in memories where the energetic particles strike the sensitive region in the transistors mainly under abnormal conditions such as high radiation, high temperature, and high pressure. These soft errors can cause bit value changes without any notification to the controller, affect the stability of the system, and result in catastrophic consequences. First, we investigate and analyze the effects of soft errors in the ILC systems. Our analytical study shows that when a single soft error occurs in the output data from the ILC, the performance of the learning control is significantly degraded. Second, we propose novel learning methods by incorporating the existing techniques across the system abstraction levels in the ILC to compensate for soft-error-induced incorrect output. The occurrence of soft errors is estimated by using a monotonic convergence of the erroneous outputs in a cross-layer manner, and our proposed methods can significantly reduce these negative impacts on the system performance. Under the assumption of soft error occurrence, our analytic study has proved the convergence of the proposed methods in the ILC systems and our simulation results show the effectiveness of the proposed methods to efficiently reduce the impacts of soft-error-induced outputs in the ILC systems.

Soft Error in Saddle Fin Based DRAM

Soft error effects due to the alpha particle and terrestrial neutron strike are investigated in a saddle fin DRAM using the 3D TCAD simulation. The strike location and angle dependency are investigated, and the worst-case incidence condition is studied. As the strike time is relevant for the error pattern, the strike during the write period is found to have minor effect, but the strike during the hold period shows data corruption. The inter-active disturbance is effectively suppressed due to the shallow trench isolation, but the inter-active ionizing radiation disturbance can be a potential risk as the capacitance of the storage capacitor continues to reduce with the DRAM technology scaling.

Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications

This work presents a half-select free 12T SRAM cell with Data-Dependent Feedback Cutting approach to improve the write ability and isolated read path to enhance the read stability. The enhanced read and write ability is 1.95× and 2.84× larger respectively than that of the conventional 6T cell at 0.4 V. The half-select free behavior of proposed cell using the cross-point read/write structure facilitates the bit-interleaving memory architecture to effectively reduce the multi-bits soft error occurrence. The incorporated PMOS stacking effect in inverter pairs of the proposed cell offers the reduced leakage power which is 0.59× to that of 6T, at 0.4 V supply. To further minimize the leakage power at array level, the bit lines between two adjacent cells have been shared that consumes only 0.38× leakage power than that of the conventional 6T array for a 1 KB macro. Moreover, a Reconfigurable FPGA architecture is proposed for low power applications. The simulated static and active power consumption of 12T SRAM based reconfigurable FPGA is 0.22× and 0.45× when compared with the regular 12T FPGA. Finally, a Double Adjacent-bits Error Detection and Correction (DAEDC) scheme is suggested for the proposed bit-interleaved 12T SRAM array, to reduce the soft error effects.

Dependability Analysis of Data Storage Systems in Presence of Soft Errors

In recent years, high availability and reliability of Data Storage Systems (DSS) have been significantly threatened by soft errors occurring in storage controllers. Due to their specific functionality and hardware-software stack, error propagation and manifestation in DSS is quite different from general-purpose computing architectures. To our knowledge, no previous study has examined the system-level effects of soft errors on the availability and reliability of data storage systems. In this paper, we first analyze the effects of soft errors occurring in the server processors of storage controllers on the entire storage system dependability. To this end, we implemented the major functions of a typical data storage system controller, running on a full stack of storage system operating system, and developed a framework to perform fault injection experiments using a full system simulator. We then propose a new metric, Storage System Vulnerability Factor (SSVF), to accurately capture the impact of soft errors in storage systems. By conducting extensive experiments, it is revealed that depending on the controller configuration, up to 40% of cache memory contains end-user data where any unrecoverable soft errors in this part will result in Data Loss (DL) in an irreversible manner. However, soft errors in the rest of cache memory filled by Operating System (OS) and storage applications will result in Data Unavailability (DU) at the storage system level. Our analysis also shows that Detectable Unrecoverable Errors (DUEs) on the cache data field are the major cause of DU in storage systems, while Silent Data Corruptions (SDCs) in the cache tag and data field are mainly the cause of DL in storage systems.

Correction to “Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects”

In the above paper [1] , the funding information should read “This work was supported in part by the Hongik University New Faculty Research Support Fund, and in part by the National Research Foundation of Korea (NRF) grant funded by the Korean Government [Ministry of Science, ICT and Future Planning (MSIP)] under Grant NRF-2017R1C1B5017414.”

Design and Implementation of Configuration Memory SEU-Tolerant Viterbi Decoders in SRAM-Based FPGAs

A Viterbi decoder is used in many communication receivers to efficiently decode the received signal that has been convolutional encoded in the transmitter. This decoding corrects errors that occur due to noise and other imperfections in the channel and is key to achieve a low bit error rate. If the decoder is implemented on a SRAM-based field-programmable gate array (SRAM-FPGA), the radiation-induced soft errors can affect the operation of the Viterbi decoder by corrupting the configuration memory, which can change the circuit functionality and will not be corrected unless the FPGA is reconfigured. This makes the protection of Viterbi decoders implemented on SRAM-based FPGAs an important issue. In this paper, first, fault injection experiments are conducted to study the effects of soft errors on the configuration memory of an SRAM-FPGA implemented Viterbi decoder. Then, an efficient protection technique is proposed and evaluated showing that it can provide an efficient protection with a lower resource usage than the traditional triple modular redundancy approach.