Effective Oxide Charge Research Articles

Electrical characteristics of atomic layer deposited Au/Ti/HfO2/n-GaAs MIS diodes in the wide temperature range

Au/Ti/HfO2/n-GaAs MIS (metal/insulating layer/semiconductor) diodes were fabricated by atomic layer deposition technique and their electrical properties were investigated in detail by the help of current–voltage (I–V) and admittance measurements in the temperature range of 60–320 K. Together with the surface morphology analysis on the HfO2 thin-film layer, main electrical parameters such as series resistance (Rs), zero bias barrier height (ΦBo), ideality factor (n), impedance (Z) and phase angle were determined and effects of temperature on these parameters of the MIS diodes were discussed. The evaluation of I–V data exhibits a decrease in Rs and ΦBo, however an increase in n, with a decrease in temperature. Temperature-dependent conductance (G) and capacitance (C) characteristics of the MIS diode were investigated at 1000 kHz in the voltage interval in between − 3 and 2 V. G and C values were found in a direct relation with the change in temperature. On the other hand, Z values showed an inverse proportionality with temperature. The phase angle versus voltage plots were evaluated at different temperatures (60–320 K) at 1000 kHz and the obtained results indicated that the device behaves more capacitive in the voltage range of − 3 V and about 0.4 V for all temperature, and phase angle decreases with increasing temperature from 0.4 to 1.6 V. In addition, the interface state density (Dit), the effective oxide charge density (Qeff) and effective number of charges per unit area (Neff) of the fabricated diodes were investigated over temperature range 60–320 K in which these values were found in a decreasing trend with increasing temperature.

Post-deposition-annealed lanthanum-doped cerium oxide thin films: structural and electrical properties

The metal-organic-decomposed lanthanum cerium oxide (LaCeO2) solution was spin-coated on p-type Si substrate to form thin films. The method of microwave-assisted annealing was adopted to modify the surface properties of the deposited thin films. The post-deposition annealing (PDA) at different microwave powers and thermal annealing temperature of 400 °C was performed on LaCeO2 thin films spin-coated on Si. Influence of this PDA on structural and electrical properties of deposited LaCeO2 thin films was studied and compared. X-ray diffraction (XRD) and Fourier transform infrared spectroscopy (FTIR) results reveal the great improvement in the structural properties in terms of removal of residual impurities from LaCeO2 films, reduced roughness and improvement in crystalline properties as compared to those of hot-plate-annealed samples. The electrical properties of Al/LaCeO2/Si stack were also studied. The different electrical parameters such as k value, interface trap density (Dit) and effective oxide charges (Qeff) were extracted and found to be improved with the increase in microwave annealing power.

Influence of frequency and gamma irradiation on the electrical characteristics of Er2O3, Gd2O3, Yb2O3, and HfO2 MOS-based devices

The unique physical, chemical, and electronic properties of rare earth oxides have been of immense interest to replace SiO2 as a dielectric material in metal–oxide–semiconductor (MOS)-based sensors applications to accurately measure the radiation dosage and increase sensor sensitivities in as diverse applications as space radiation, nuclear physics, medical diagnostics, radiation cancer therapy, and personal dosimetry devices. Hence, the electrical characteristics of oxides prior to and after irradiation of MOS-based devices are needed since they are the backbone of the devices such as MOSFETs and ICs. In addition, an understanding of the behaviour of high-k dielectric oxides in an MOS configuration is necessary since the radiation-induced damage occurs in the bulk oxide film and/or near the oxide–semiconductor interface resulting in creation of lattice defects. Hence, MOS structures with the rare earth oxides of Er2O3, Gd2O3, Yb2O3, and a transition metal oxide of HfO2 were produced by RF magnetron sputtering to determine (a) the structure of the films, (b) dielectric constants, (c) capacitance versus voltage behaviour of Er2O3, Gd2O3, Yb2O3, and HfO2 prior to and after irradiation of the devices in the dose range of 0–76 Gy. The experimental results were analysed with a theoretical framework on the energy band diagram and the radiation effects on the electrical characteristics of the MOS capacitors. The characteristics of the devices were evaluated by using effective oxide charge density ( $$ Q_{\text{EFF}} $$ ), variation in the oxide trapped charge density ( $$ \Delta N_{\text{ox}} $$ ), and interface trapped charge density ( $$ \Delta N_{\text{it}} $$ ). In addition, barrier height ( $$ \phi_{\text{b}} $$ ), image force barrier lowering ( $$ \Delta \phi_{\text{b}} $$ ), acceptor concentration ( $$ N_{\text{a}} $$ ) were calculated before and after irradiation and examined the nature of interface states. The radiation responses of the Er2O3 and HfO2 MOS capacitors did not show a stable behaviour with an increase in radiation dose due to possible neutral electron trap centres. Contrary to expectations, we infer that more negative charges are trapped in Gd2O3-based device than positive charges with an increase in radiation dose. The C–V curves of the Yb2O3 MOS capacitor shifted in the same direction at both 100 kHz and 1 MHz, and as expected, positive charge traps in the structure are more efficient than negative charges. The observed sensitivities of Yb2O3 MOS capacitors are 4–7 times higher than those of SiO2, and the sensitivities of the Yb2O3 MOS capacitors with a total radiation dose of 70 Gy were found to be around 28.08 mV/Gy at both 100 kHZ and 1 MHz frequencies. The Yb2O3 appears to be a promising dielectric candidate for developing a new generation of radiation sensors with an excellent interface quality when compared to rare earth mixed oxides such as silicates, transition metal oxides, and the silicates based on transition metals, Al2O3, and BiFeO3. Our review of the literature suggests that while the radiation damage has been assessed comprehensively based on the C–V characteristics, microstructural characterization of the irradiated films and their interfaces is lacking even though the quality of oxide/Si interface is the most important feature of the devices. The electrical data should be correlated with the inferences from XPS, AFM, TEM, XRD, and other techniques. Further progress requires selection and validation of material properties based on theoretical calculations and predications, utilization of diverse thin film processing and characterization techniques, determining the effect of thickness on the properties of MOS capacitors, a thorough understanding of the interfaces, effect of frequency on the MOS capacitors and the interface characteristics, effect of radiation on the physical, interfacial, and electrical characteristics of MOS capacitors, and preparation and characterization of sensors based on thin films of novel mixed oxides and silicates of different chemistries.

Oxide charge evolution under crystallization of amorphous Li–Nb–O films

Li–Nb–O amorphous films were deposited onto Si substrates by the radio-frequency magnetron sputtering method in an Ar environment and an Ar(60%)+O 2 (40%) gas mixture. A positive effective fixed oxide charge Q eff having negative, -Q eff , and positive, +Q eff , components, exists in the as-grown heterostructures. -Q eff is located near the substrate/film interface, whereas + Q eff is determined by a deficit of Li and O (vacancies) in the bulk of Li–Nb–O films. As-grown films crystallized under thermal annealing (TA) at temperatures up to 600 °C and revealed the formation of polycrystalline LiNbO 3 . TA at about 520 °C resulted in the formation of the second phase LiNb 3 O 8 , increasing + Q eff , and compensating -Q eff entirely. The dielectric constants of the as-grown films exhibit two peaks at the annealing temperatures of 450 °C and 550 °C, which are attributed to the total crystallization and recrystallization of the LN films under TA, respectively.

Alternate lanthanum oxide/silicon oxynitride-based gate stack performance enhancement due to ultrathin oxynitride interfacial layer for CMOS applications

Metal–insulator–semiconductor (MIS)-based Pt/La2O3/SiOXNY/p-Si/Pt structures are fabricated using ultrathin silicon oxynitride (SiOXNY ~ 4 nm) interfacial layer underneath of lanthanum (III) oxide (La2O3 ~ 7.8 nm) with Pt as gate electrode for CMOS applications. Capacitance–voltage (C–V) characteristics of Pt/La2O3/SiOXNY/p-Si/Pt at 500 kHz showed a positive gate bias threshold voltage (Vth) shift of ~ 0.43 V (~ 43.8%) and flat-band (Vfb) shift of ~ 1.24 V (~ 42.3%) as compared to Pt/La2O3/p-Si/Pt MIS structures, attributing to the reduction in effective positive oxide charges at La2O3/SiOXNY/Si gate stack. Likewise, conductance–voltage (G–V) characteristics show ~ 0.56 (~ 44.4%) reduction in FWHM for Pt/La2O3/SiOXNY/p-Si/Pt as compared to Pt/La2O3/p-Si/Pt MIS structures revealing the reduction in interface states at La2O3/SiOXNY/Si interface. There is a considerable reduction of effective oxide charge concentration (Neff) ~ 3.99 × 1010 cm−2 by (~ 15.2%) and ~ 56.8% lower gate leakage current density ~ 4.47 × 10−7 A/cm2 (|J|–V) at − 1 V for SiOXNY based MIS structures w.r.t its counterpart. Capacitance–time (C–t) characteristics, constant voltage stress (CVS) and temperature measurements for C–V and |J|–V demonstrate the considerable retention ~ 12 years, electrical improvement and reliability of MIS structures. The depth profile analysis X-ray photoelectron spectroscopy (XPS) for SiOXNY/Si gate stack clearly reveals that less nitrogen concentration in bulk than SiOXNY/Si interface. Atomic force microscopy (AFM) micrographs of La2O3/Si and SiOXNY/Si showed the significantly lesser r.m.s roughness of ~ 1.11 ± 0.39 nm and ~ 0.97 ± 0.11 nm, respectively. Thus, the ultrathin SiOXNY interfacial layer underneath of La2O3 demonstrates a significantly improved electrical performance and prelude the gate stack strong potential for reliable CMOS logic devices and integrated circuits.

Effective Charge in LiNbO3 Films Fabricated by Radio-Frequency Magnetron Sputtering Method

Amorphous Li–Nb–O films were deposited onto Si substrates by radio-frequency magnetron sputtering method. The fabricated heterostructures demonstrated the presence of effective oxide charge Qeff having both negative and positive components. Thermal annealing (TA) of as-grown heterostructures leads to the crystallization of a Li–Nb–O system with the formation of LiNbO3 films. The Qeff changes with TA, reaching a minimum at the annealing temperature of about 470°C, corresponding to the entire film’s crystallization.

Effect of sweeping direction on the capacitance−voltage behavior of sputtered SiO2/4H-SiC metal-oxide semiconductors after nitric oxide post-deposition annealing

The effect of sweeping direction on the capacitance–voltage (C–V) behavior of sputtered SiO2/4H-silicon carbide (SiC) metal-oxide semiconductor capacitors was investigated. Nitric oxide post-deposition annealing was conducted for the sputtered SiO2 on 4H-SiC. The sweeping direction of the measurement changed the C–V behavior and effective oxide charge density (Qeff) because of trapped electrons at the accumulation and detrapped electrons at the depletion. The nitrogen atoms near interface between SiO2 and 4H-SiC as a result of nitric oxide post-deposition annealing shifted the flat-band voltage in the negative direction. When the C–V was measured from depletion to accumulation, the absolute value of the Qeff after 60 min long annealing, 3.465 × 1010 cm−2 was less than that of the Qeff after 30 min long annealing, −2.912 × 1011 cm−2. The mechanisms of the nitric oxide post-deposition annealing on sputtered SiO2 on 4H-SiC are film densification and nitrogen passivation of the defects.

Positive flatband voltage shift in phosphorus doped SiO2/N-type 4H-SiC MOS capacitors under high field electron injection

The effect of phosphorus inclusion on different bias stress at high electric field on phosphorus doped SiO2 is investigated by electrical measurements of SiC MOS capacitors. 1 MHz measurements with (1) different bias hold time (up to 999 s at room and high temperature of 250 °C), (2) different applied gate voltage (10, 20 and 30 V without stress time) and (3) different bias hold time at high voltage (30 V) were taken to observe the evolution of flatband voltage, effective oxide charge density and interface state density. In this investigation, the characteristics were measured in both sweep directions and compared to those obtained from undoped SiO2 samples. At 250 °C, the flatband voltage of phosphorus-doped SiO2 samples shows a significant shift to the positive with increasing bias hold time. Similar trends are observed with the characteristics obtained at room temperature, but the shifts are less significant. Both undoped and phosphorus-doped samples show positive flatband shift when a higher bias was applied for longer hold times, but the latter demonstrated more significant changes. We conclude that the phosphorus ions increase the instability of the electrical characteristics related to the generation of mobile charges in the SiO2, resulting in the injection of electrons from the semiconductor to the oxide. Therefore, the accumulated negative charge in phosphorus-doped SiO2 resulting from the injection of electrons, which is enhanced by the mobile charge, is responsible for the enhanced positive shift in and characteristics.

A Reliable Technology for Advanced SiC-MOS Devices Based on Fabrication of High Quality Silicon Oxide Layers by Converting a-Si

An alternative technological approach is proposed to obtain a SiO2 film on SiC using processes that finally reduce the effective fabrication costs. Accordingly, we report achieving of a high-quality oxide on 4H-SiC substrate using a process flow that consists in a preliminary deposition by sputtering, at room temperature, of an amorphous Si thin layer, followed by its oxidation at a relative low temperature (1100 °C) for SiC MOS technology. The X-ray reflectivity measurements demonstrated that the resulted oxide has a comparable roughness with the one thermally grown and presents the advantage of an almost threefold thinner interfacial layer. The improvement of the oxide/semiconductor interface was further validated by the electrical investigation of the fabricated MOS structures, where a significant diminishing of the effective oxide charge density, interface traps density, and near interface oxide traps density was assessed. Thus, we demonstrated that, for a specified thickness of the oxide layer on SiC, the proposed technological flow not only significantly reduces the standard duration of the process necessary and consequently the associated fabrication cost, but, more important, leads to superior oxides and interfaces, in terms of both micro-physical and electrical properties.

Gate Oxide Electrical Stability of p-type Diamond MOS Capacitors

This paper shows the effect of performing consecutive measurement prior to negative bias stress instability (NBSI) on diamond metal–oxide–semiconductor capacitor (MOSCAP). For the first time, time-dependent stress tests have been carried out in order to investigate the stability of the flatband voltage ( ${V}_{\text {FB}}$ ) of MOSCAPs through capacitance–voltage ( CV ) measurements. Two tests have been performed. In the first test, consecutive CV measurements with the device biased from deep depletion to the accumulation regime were performed to monitor the recovery of the ${V}_{\text {FB}}$ . In the second test, NBSI technique has been applied. ${V}_{\text {FB}}$ stability has been measured by means of a time-dependent bias stress in which the device was polarized at a fixed negative voltage for a specific time interval prior to performing the next CV measurement. As ${V}_{\text {FB}}$ is directly connected to the effective oxide charge ( ${N}_{\text {eff}}$ ), the two different tests allowed the extraction of total amount of ${N}_{\text {eff}}$ that interfered during the measurements. The result observed shows that the postoxidation annealing process induces a strong enhancement of the MOSCAP stability together with a decrease of ${N}_{\text {eff}}$

Analysis of surface radiation damage effects at HL-LHC fluences: Comparison of different technology options

Radiation damage effects at High Luminosity LHC (HL-LHC) fluences greater than 2.2×1016n∕cm2 1 MeV equivalent and total ionizing doses (TID) greater than 1 Grad will impose very stringent constraints in terms of radiation resistance of solid-state detectors. To cope with this design challenge, TCAD tools can be used to study different technology and design options, in order to optimize the performance of silicon detectors in terms of inter-electrode isolation and charge collection properties. A comprehensive modeling approach based on combined bulk and surface damage effects accounting for a limited number of measurable parameters needs therefore to be developed and validated over different technology options. In this work, we mainly focus on the effects of surface damage on detectors fabricated on p-type substrates by different providers. Actually, starting from standard test structure measurements (i.e. MOS capacitors, gated diodes), the integrated interface trap state density (NIT) and the oxide charge (QOX) can be extracted for different vendors and used as input parameter to the simulation tools. Test structures under study include MOS capacitors, gated-diodes, fabricated both at Hamamatsu Photonics (Japan) and at Infineon (Austria). Using High-Frequency (HF) and Quasi-Static (QS) C–V characteristics and current–voltage (I–V) measurements, the effective oxide charge density (NEFF), the surface generation velocity (s0) and the interface trap density (DIT) have been determined and compared for the two technologies before and after irradiation with X-rays with doses ranging from 0.05 to 20 Mrad(SiO2). A detailed simulation analysis on MOS capacitor capacitances and gated diode currents has been carried out, varying the previously mentioned parameters, with the aim to evaluate the effects of oxide charge density and interface trap density increase with the dose. The separate effects of different types of interface trap states have been considered as well, by varying one by one the total density of donor- and acceptor-type trap states, respectively. The effects of different trap energy distributions and capture cross sections have been evaluated within Synopsys Sentaurus TCAD device simulator by means of steady-state, AC and transient analyses. The good agreement obtained for both vendors would support the use of the model as a predictive tool to optimize the design and the operation of novel solid-state detectors in the HL-LHC scenario.

Understanding of post deposition annealing and substrate temperature effects on structural and electrical properties of Gd2O3 MOS capacitor

The purpose of this study is to understand the effects of substrate temperature (ST) and post deposition annealing (PDA) on the structural-electrical properties of Gd2O3 film and to evaluate the electrical performances of the MOS based devices formed with this dielectric. The Gd2O3/Si structures were annealed at 500, 600, 700, and 800 °C under N2 ambient after the films were grown on heated p-Si substrate at various temperatures ranged from 20 to 300 °C by RF magnetron sputtering. For any given ST, the crystallization/grain size increased with increasing PDA temperature. The bump in the accumulation region or continuous decrease in the capacitance values of the inversion region of the C–V curves for 800 °C PDA was not observed. The lowest effective oxide charge density (Qeff) value was obtained to be − 1.13 × 1011 cm−2 from the MOS capacitor with Gd2O3, which is grown on heated Si at 300 °C and annealed at 800 °C. The density of the interface states (Dit) was found to be in the range of 0.84 × 1011 to 1.50 × 1011 eV−1 cm−2. The highest dielectric constant (e) and barrier height $$({\Phi _B})$$ values were found to be 14.46 and 3.68, which are obtained for 20 °C ST and 800 °C PDA. The results show that the negative charge trapping in the oxide layer is generally more than that of the positive, but, it is reverse of this situation at the interface. The leakage current density decreased after 20 °C ST, but no significant change was observed for other ST values.

Fabrication and characterization of n-Si/SiON/metal gate structure for future MOS technology

We present the fabrication and characterization of n-Si/SiON/metal (metal–oxide–semiconductor (MOS)) gate structure with silicon oxynitride (SiON) as insulating layer and different metal films such as Aluminium (Al), Titanium nitride (TiN) and Platinum (Pt) as gate electrode. Cheung’s method has been used to calculate the barrier height (ϕbo) and ideality factor (η) of these three different diodes varying in different metal electrode types. The interface state density (Dit), dielectric constant (k), effective oxide charge (Qeff) and work function (Φm) have also been extracted from the capacitance–voltage (C–V) experimental data. A gradual improvement in various parameters for n-Si/SiON/metal gate stack has been observed after annealing the SiON film under controlled conditions e.g., TiN metal gate electrode shows good electrical characteristics with improved ideality factor (1.7) and barrier height (0.69 eV) over the Al and Pt/Ti gate electrodes due to the modified interface chemistry. The extracted Φm for TiN gate electrode is ~ 5.13 eV which is in good agreement with the previous results reported in literature. The value of Dit reduces, whereas the value of k increases upon post deposition annealing (PDA) for all the metal gate electrodes. An increase in Dit causes an increase in the η for Al and Pt/Ti metal gates as compared to TiN metal gate. The influences of PDA process on the electrical characteristics of n-Si/SiON/metal MOS diodes have also been investigated for as-deposited and annealed MOS diode.

Fabrication and characterization of AlN metal–insulator–semiconductor grown Si substrate

An experimental investigation was conducted to explore the effect of inserting a single AlGaN interlayer between AlN epilayer and GaN/AlN heterostructures on Si (111) grown by molecular beam epitaxy (MBE). It is confirmed from the scanning electron microscopy (SEM) that the AlGaN interlayer has a remarkable effect on reducing the tensile stress and dislocation density in AlN top layer. Capacitance–voltage (C–V) measurements were conducted to study the electrical properties of AlN/GaN heterostructures. While deriving the findings through the calculation it is suggested that the AlGaN interlayer can significantly reduce the value of effective oxide charge density and total effective number of charges per unit area which are [Formula: see text] and [Formula: see text], respectively.

Effects of post-deposition annealing on sputtered SiO2/4H-SiC metal-oxide-semiconductor

Reactive sputtering followed by N2, NH3, O2, and NO post-deposition annealing (PDA) of SiO2 on 4H-SiC was investigated in this study. The results of ellipsometry, an etching test, and X-ray photoemission spectroscopy showed that N2 and NH3 PDA nitrified the SiO2. Devices using N2 and NH3 PDA exhibited a high gate leakage current and low breakdown field due to oxygen vacancies and incomplete oxynitride. SiO2/4H-SiC MOS capacitors were also fabricated and their electrical characteristics measured. The average breakdown fields of the devices using N2, NH3, O2, and NO PDA were 0.12, 0.17, 4.71 and 2.63 MV/cm, respectively. The shifts in the flat-band voltage after O2 and NO PDA were 0.95 and −2.56 V, respectively, compared with the theoretical value. The extracted effective oxide charge was −4.11 × 1011 cm−2 for O2 PDA and 1.11 × 1012 cm−2 for NO PDA. NO PDA for 2 h at 1200 °C shifted the capacitance–voltage curve in the negative direction. The oxygen containing PDA showed better electrical properties than non-oxygen PDA. The sputtering method described can be applied to 4H-SiC MOS fabrication.

Effects of thermal oxidation duration on the structural and electrical properties of Nd2O3/Si system

A study on the growth, structure and electrical properties of Nd2O3 was carried out experimentally on RF sputtered thin film on Si followed by thermal oxidation at 700 °C at different oxidation durations (5, 10, 15 and 20 min). The structural and chemical properties were studied by X-ray diffraction analysis, Fourier transform infrared analysis, Raman analysis and high resolution transmission electron microscopy analysis. The formation of cubic-Nd2O3, orthorhombic-Nd2Si2O7, monoclinic-SiO2, tetragonal-SiO2 and hexagonal-SiO2 was detected. A single interfacial layer was detected for the sample oxidized at 15 min and double interfacial layers were detected for the samples oxidized at 5, 10 and 20 min. The sample oxidized at 15 min possessed the best electrical properties which were attributed by the highest Nd2O3 intensity, largest SiO2 crystallite structure, thinnest interfacial and oxide layer, highest barrier height, lowest effective oxide charges, slow trap density and average interface trap density.

Influence of applied voltage on the physical and electrical properties of anodic Sm 2 O 3 thin films on Si in 0.01 M NaOH solution

Formation of anodic samarium oxide thin film by anodisation of 15 nm thin sputtered samarium metal on silicon substrate was systematically investigated. Sputtered Sm on Si substrate was followed by anodisation in 0.01 M NaOH (pH 11) at various applied voltages (10, 15, 20, and 25 V). All anodisation processes were performed for 10 min at room temperature in the bath with constant stirring. The crystallinity of Sm2O3 film was evaluated by X-ray diffraction analysis. The crystallite size of Sm2O3 was calculated by Scherrer equation. The cross-section of 20 V sample was examined by high-resolution transmission electron microscope. The sample anodised at 20 V demonstrated the highest electrical breakdown field of 9.50 MV/cm at 10-4 A/cm2. This is attributed to the lowest effective oxide charge, slow trap charge density, average interface trap density, and total interface trap density.

Preparation of rare earth CeO2 thin films using metal organic decomposition method for metal-oxide–semiconductor capacitors

Investigation of metal organic decomposed rare earth cerium oxide thin films deposited on Si substrate by sol–gel spin coating technique was carried out. The structural properties have been examined by using XRD, Fourier transform infrared spectroscopy (FTIR), field emission scanning electron microscopy (FESEM) and atomic force microscopy (AFM). The XRD confirms the cubic phase of CeO2 thin films with (111) plane observed at 28.54°. The FTIR and EDAX spectra confirm the formation of CeO2 films with atomic percentage of 19.39 and 54.82% of Ce and O2, respectively. Thickness of 60.11 nm of CeO2 film measured by cross sectional FESEM image, the average roughness of ~0.6 nm of 400 °C annealed CeO2 films were observed from AFM micrograph. The MOS capacitors were fabricated by using Ti/Au bilayer metal contact depositing by E-beam evaporator on CeO2/Si thin film for electrical measurements. Capacitance and conductance voltage measurement was carried out to determine the effective oxide charges (Qeff), interface trap density (Dit) and dielectric constant (k) and are 2.48 × 1012 cm−2, 1.26 × 1012 eV−1cm−2 and ~39, respectively. The effective metal work function of 5.68 for Ti/Au bilayer is observed to be higher than the work function of Ti or Au metals in vacuum.

Argon Annealed ALD-ZrO2/SiON Gate Stack for Advanced CMOS Devices

We report on the fabrication of ultra-thin silicon oxynitride (SiON ~ 5.34 nm) as sacrificial layer (SL) for n-Si/ALD-ZrO2 gate stack followed by the post deposition annealing (PDA) of ZrO2 in argon ambient. The surface morphological studies include atomic force microscopy (AFM) and field emission scanning electron microscopy (FESEM) whereas the thicknesses of the grown films were confirmed by both ellipsometry and FESEM cross-sectional studies. The surface topographical study suggests the r.m.s. roughness of 0.796 nm for nano zirconia film after rapid thermal annealing (RTA). Electrical parameters such as dielectric constant (K), effective oxide thickness (EOT), leakage current density (J), effective oxide charge (Qeff) and series resistance (Rs) were extracted through C-V and I-V measurements and the determined values of K, J, EOT, Qeff and Rs at 100 KHz are 26, 8.75 × 10-9 A/cm2, 2.1 nm, 0.42 × 1013 cm-2 and 4.54 KΩ respectively. The concept of SiON SL has significantly suppressed the existing unacceptable gate leakage current and the interfacial traps owing to appropriate segregation of nitrogen at the interface of SiON/ZrO2. Moreover, PDA of ZrO2 film in argon ambient at 5000 C has reduced the r.m.s. roughness and also contributed to the overall reduction of gate leakage current density, thereby, making ALD-ZrO2/SiON gate stack quite attractive for advanced CMOS devices.

Argon Annealed ALD-ZrO2/SiON Gate Stack for Advanced CMOS Devices

Now-a-days, high-k dielectric materials are in demand as they not only inhibit direct tunneling but also ensures relatively thicker oxides. To replace SiO2 as gate dielectric, a number of high-k materials have been extensively studied such as aluminum oxide (Al2O3), zirconium dioxide (ZrO2), cerium oxide (CeO2), hafnium oxide (HfO2) and titanium dioxide (TiO2). Among them, ZrO2 is one of the most outstanding candidates due to its excellent chemical, physical and electrical properties such as good thermodynamic stability with silicon, high dielectric constant, high melting point, high refractive index, and sufficient band gap. Atomic layer deposition (ALD) method having the benefit of low temperature deposition and extremely precise thickness control has been utilized for the deposition of ZrO2 film. Additionally, the post deposition annealing (PDA) of ZrO2in argon (Ar) ambient has been performed along with Ti-Pt as bilayer metal gate. Taking into consideration the state-of-the-art research progress, we report the fabrication of ultra-thin silicon oxynitride (SiON) as a sacrificial layer (SL) for n-Si/ALD-ZrO2 gate stackfollowed by post deposition annealing (PDA) of ZrO2 in argon (Ar) ambient. The surface roughness for the Ar annealed ZrO2 film measured using atomic force microscopy (AFM) was found to be 0.796 nm whereas the thicknesses of SiON SL ~ 5.34 nm and ZrO2 film ~ 11.63 nm were corroborated by field emission scanning electron microscope (FESEM) and spectroscopic ellipsometer (SE). Electrical characterizations such as capacitance voltage and current voltage measurements indicates the improved results for n-Si/ALD-ZrO2/Ti-Pt MOS capacitor in terms of various performance parameters such as dielectric constant (K), effective oxide thickness (EOT), leakage current density (J), effective oxide charge (Qeff) and series resistance (Rs) and their determined values are 26, 2.1 nm, 8.75 × 10-9 A/cm2, 0.42 × 1013 cm-2 and 4.54 KΩ respectively. The noble concept of SiON SL along with the PDA of ZrO2 in Ar ambient can enable the further scaling of n-Si/SiON/ZrO2 gate stack without the adverse effects of gate leakage current. Some of the important results obtained from the reported work have been exemplified in the figures below. Figure 1