Effect Of Gate Bias Research Articles

Joint effect of gate bias and light illumination on metallic LaAlO3/SrTiO3 interface

We presented a systemic investigation on the joint effect of gate bias and light illumination on a metallic LaAlO3/SrTiO3 interface in the temperature range from 15 K to 300 K. We showed that the photo excitation significantly enhanced the gating effect for the metallic two-dimensional electron gas. However, its effect is strongly temperature dependent; it is strong at low and high temperatures, and weak in the intermediate temperature range. There are evidences that the amplified gating effect stemmed from enhanced carrier depletion while the Hall mobility remains nearly unaffected. Acceleration of the gating process, together with a training effect marked by a strong dependence on gating history of the getting effect, is induced by repeating the electric cycling, indicating atomic reconfiguration due to oxygen migration and the memory of the migration paths.

Effect of liquid gate bias rising time in pH sensors based on Si nanowire ion sensitive field effect transistors

In this study, we investigate the effect of rising time (TR) of liquid gate bias (VLG) on transient responses in pH sensors based on Si nanowire ion-sensitive field-effect transistors (ISFETs). As TR becomes shorter and pH values decrease, the ISFET current takes a longer time to saturate to the pH-dependent steady-state value. By correlating VLG with the internal gate-to-source voltage of the ISFET, we found that this effect occurs when the drift/diffusion of mobile ions in analytes in response to VLG is delayed. This gives us useful insight on the design of ISFET-based point-of-care circuits and systems, particularly with respect to determining an appropriate rising time for the liquid gate bias.

Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data.

The total ionizing dose response of a DSOI 4Kb SRAM

A 4K-bit SRAM with 0.2um Double Fully-Depleted Silicon-On-Insulator (DSOI) CMOS process is designed to examine circuit total ionizing dose (TID) and the back gate bias effect. Preview researches show that MOSFET electrical parameter shift due to TID damage can be compensated by back gate bias of the FDSOI technology. We can control the NMOS/PMOS back gate separately and discretionarily with DSOI structure which could improve circuit radiation tolerance. TID experiment results show that the total ionizing dose capability of the 4Kb SRAM test chip is above 1M rad (Si).

CMOS Class-E 전력증폭기의 Cascode 구조에 대한 게이트바이어스 효과 분석

CMOS Class-E 전력증폭기의 Cascode 구조에 대한 게이트바이어스 효과 분석

Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

A generalized 2-D analytical model of gate threshold voltage for multiple material gate Tunneling FET (TFET) structures is derived. The model can also be used for calculating threshold voltage of a single metal gate TFET. Surface potential model of a triple material double gate TFET has been developed by applying Gauss's law in the device. From the potential model, physics-based model of gate threshold voltage has been derived by exploring the transition between linear to quasi-exponential dependence of drain current on applied gate bias. The model includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters. The accuracy of the proposed model is verified by comparing the results predicted by the proposed model to the results of the numerical model developed in Silvaco, Atlas.

Highly sensitive MoTe2 chemical sensor with fast recovery rate through gate biasing

The unique properties of two dimensional (2D) materials make them promising candidates for chemical and biological sensing applications. However, most 2D nanomaterial sensors suffer very long recovery time due to slow molecular desorption at room temperature. Here, we report a highly sensitive molybdenum ditelluride (MoTe2) gas sensor for NO2 and NH3 detection with greatly enhanced recovery rate. The effects of gate bias on sensing performance have been systematically studied. It is found that the recovery kinetics can be effectively adjusted by biasing the sensor to different gate voltages. Under the optimum biasing potential, the MoTe2 sensor can achieve more than 90% recovery after each sensing cycle well within 10 min at room temperature. The results demonstrate the potential of MoTe2 as a promising candidate for high-performance chemical sensors. The idea of exploiting gate bias to adjust molecular desorption kinetics can be readily applied to much wider sensing platforms based on 2D nanomaterials.

Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications

In this work, the effect of gate metal work function engineering (GME), gate bias and drain bias on the bias dependent parasitic capacitances has been studied. Further, RF Figure of merits (FOMs) such as power gains, cut-off frequency (fT), maximum oscillation frequency (fMax) and intrinsic delay of hetero-dielectric gate-metal-engineered gate-all-around tunnel FET (HD-GME-GAA-TFET) are studied and compared with HD-GAA-TFET. Simulation results show an appreciable improvement in RF FOMs with the application of GME architecture on GAA TFET. Further, it has been observed that GME exhibits 3.76 times enhancement and 0.017 times reduction in cut-off frequency and intrinsic delay respectively as we increase the work function difference, which makes it a promising candidate for low power switching applications. Moreover, the small signal Y-parameters have also been studied which indicates that HD-GME-GAA-TFET is a promising candidate for RF/microwave applications. All the simulations have been done using ATLAS device simulator.

Analysis of electrostatic doped Schottky barrier carbon nanotube FET for low power applications

This paper presents the analysis of electrostatic doped Schottky barrier carbon nanotube FET (ED-SBCNTFET) for low power applications. Electrostatic doping is introduced in intrinsic CNT as a channel material which reduces the process complexity; moreover dynamic configuration provides symmetric transfer characteristics for n-type and p-type for ED-SBCNTFET. Simulation results demonstrate that ED-SBCNTFET is better than conventional CNTFET in terms of IOFF and subthreshold swing (SS) which makes it suitable for low power applications. Simulations are performed and sensitivity analysis is carried out for CNT diameter, effective oxide thickness (EOT), high-k dielectric and polarity gate bias. It is observed that CNTs are most sensitive to diameter, since CNT with diameter 0.85 nm exhibits ION/IOFF ratio of ~109 and SS of 60.8 mv/dec whereas diameter of 0.55 nm results into ION/IOFF ratio of ~1011 with SS of 58.5 mv/dec. Optimized parameters are proposed for low power applications in terms of IOFF and SS. ED-SBCNTFET has been analysed for various process parameters and it has been demonstrated to be less sensitive to process variations.

A GaN HEMTs Nonlinear Large-Signal Statistical Model and Its Application in S-Band Power Amplifier Design

A GaN HEMTs nonlinear large-signal statistical model based on empirical equivalent circuit including nonlinear electrothermal effect and trapping effects is proposed in this letter. The electrothermal model is constructed by one stage nonlinear R-C electrothermal network, and the trapping effects is modeled by effective gate (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gseff</sub> ) bias based on Angelov model. Thirty-four GaN HEMTs from 10 batches are measured and all the parameters in the large-signal model are extracted by in-house parameters extraction program. The statistical method is modeled by combining principal component analysis, factor analysis, and multiple regressions modeling techniques. The statistical model is implemented in Agilent-ADS and the Monte Carlo simulation is fulfilled for validation. Two S-band GaN HEMT power amplifiers are designed by using the established statistical model for demonstration purpose. The results show that good accuracy have been achieved by comparing measured and Monte Carlo simulated output power (Pout) and power added efficiency (PAE). So this method is proved to be suitable for GaN HEMT power amplifier's design and yield estimation.

Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

We have studied the effect of top gate bias (VTG) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm2 intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the VTG from −15 to +15 V. By changing VTG from negative to positive, the Fermi level (EF) shifts toward conduction band edge (EC), which substantially controls the conversion of neutral vacancy to charged one (VO → VO+/VO2+ + e−/2e−), peroxide (O22−) formation or conversion of ionized interstitial (Oi2−) to neutral interstitial (Oi), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at VTG = −15 V, which gradually decreases to −0.42 V shift at VTG = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (VO+/VO2+/O22−/Oi) and/or hole trapping in the a-IGZO /interfaces.

An Investigation of Gate Pulse Induced Degradation in a-InGaZnO Thin Film Transistors.

We investigated the effects of pulsed gate bias on degradation of amorphous indium gallium zinc oxide (a-InGaZnO) thin film transistors (TFTs). The waveform composed of 0 V and 20 V produced little degradation, but the waveform composed of -20 V and 0 V produced a considerable degradation on the turn-on current in the transfer characteristics. Those instabilities were found mostly in TFTs of which the concentration of Zn is higher than the other metallic components (In, Ga). In order to explain the anomalous degradation behaviors, we propose a possible degradation model which is different from the conventional model of charge trapping. Our proposed model is related to an increase of acceptor-like states in a-InGaZnO near the source and drain electrodes. More electrons can be trapped there, and the increased potential barrier hinders current flow in the channel. The proposed model can also account for the increased frequency dispersion in C-V characteristics of our a-InGaZnO TFTs after the waveform stress.

Analytical model of gate leakage current through bilayer oxide stack in advanced MOSFET

A compact model for gate tunneling current in advanced nano-scale MOSFET has been developed on the basis of both direct and Fowler–Nordheim tunneling through dual layer Silicon oxide–Hafnium oxide stack used as gate dielectric. Calculation includes the effect of different subbands of the semiconductor conduction band those arise due to quantum confinement of charge carriers in the oxide–substrate interface. Effect of charge trapping in the bulk of the oxides and at the localized energy levels at different interfaces of the oxides has also been taken into consideration. Tunneling probability as a function of gate bias has been determined considering Wentzel–Kramers–Brillouin (WKB) approximation to account for varying potential profile. Probability amplitude of an electron for tunneling has been calculated by solving Schrodinger equations at different regions in the effective mass approximation model of class I crystal interface. Tunneling current as a function of effective oxide thickness and gate bias estimated in this model shows substantial reduction in gate leakage current if HfO2 as high-k dielectric is used along with 1nm thick SiO2 with almost negligible change in threshold voltage.

Shot noise of charge current in a quantum dot responded by rotating and oscillating magnetic fields

We have investigated the shot noise and Fano factor of the dynamic spin-polarized quantum dot under the perturbations of a rotating magnetic field (RMF), and an oscillating magnetic field (OMF) by employing the non-equilibrium Green's function approach. The shot noise is enhanced from sub-Poissonian to super-Poissonian due to the application of RMF and OMF, and it is controlled sensitively by the tilt angle θ of RMF. The magnitude of shot noise increases as the photon energy ℏω of OMF increases, and its valley eventually is reversed to peaks as the photon energy is large enough. Double-peak structure of Fano factor is exhibited as the frequency of OMF increases to cover a large regime. The Zeeman energy μ0B0 acts as an effective gate bias to exhibit resonant behavior, and novel peak emerges associated with the applied OMF.

Electrical and proximity-magnetic effects induced quantum Goos–Hänchen shift on the surface of topological insulator

We use scattering matrix method to theoretically demonstrate that the quantum Goos–Hänchen shift of the surface on three-dimensional topological insulator coated by ferromagnetic strips is sensitive to the magnitude of ferromagnetic magnetization. The dependence of quantum Goos–Hänchen shift on magnetization and gate bias is investigated by performing station phase approach. It is found that quantum Goos–Hänchen shift is positive and large under the magnetic barrier but may be positive as well as negative values under the gate bias. Furthermore, the position of quantum Goos–Hänchen peak can also be modulated by the combination of gate bias and proximity magnetic effects. Our results indicate that topological insulators are another candidates to support quantum Goos–Hänchen shift.

Experimental study of back gate bias effect and short channel effect in ultra-thin buried oxide tri-gate nanowire MOSFETs

We studied the relation between body effect factor and subthreshold slope in ultra-thin buried oxide tri-gate nanowire MOSFETs with various gate lengths, nanowire widths, and nanowire heights. As gate length decreases, body effect factor increases due to the enhancement and suppression of the short channel effect with positive and negative back gate bias voltage, respectively. The reduction of nanowire width leads to the decrease in both body effect factor and subthreshold slope resulting in trade-off relation, whereas better subthreshold slope and larger body effect factor were achieved by thinning nanowire height.

Current Collapse Suppression by Gate Field-Plate in AlGaN/GaN HEMTs

Current collapse measurements have been performed for AlGaN/GaN high-electron-mobility transistors having identical breakdown voltages but with different field plate (FP) lengths. The results indicated that applying more positive ON-state gate biases resulted in pronounced recovery in the dynamic ON-resistance for the FP device, whereas no gate-bias effects were observed for the device without FP. The mechanism responsible for the reduced current collapse by FP is proposed, in which the key role is played during ON-state by the quick field-effect recovery of partial channel depletion caused by electron trapping at AlGaN surface states between gate and drain.

Effective mobility in amorphous organic transistors: Influence of the width of the density of states

The temperature dependence of poly(3-hexylthiophene-2,5-diyl) (P3HT)/polystyrene (PS) blend organic transistor current/voltage (I–V) characteristics has been experimentally and theoretically studied. The planar transistors, realized by drop casting the P3HT/PS ink, exhibit high mobilities (over 5×10−3cm2V−1s−1) and good overall characteristics. A transistor model accounting for transport mechanisms in disordered organic materials was used to fit the measured characteristics. Using a single set of parameters, the measured effective mobility versus gate bias, either increasing or decreasing with the gate bias depending on temperature, is well reproduced over a wide temperature range (130–343K). A Gaussian density of states width of 0.045eV was determined for this P3HT/PS blend. The transistor I–V characteristics are very well described considering disordered material properties within a self-consistent transistor model.

Effect of Channel Length on the Reliability of Amorphous Indium–Gallium–Zinc Oxide Thin Film Transistors

We investigated the effect of the channel length on the reliability of amorphous indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) under the negative and positive gate bias stress. The threshold voltage (Vth) was barely changed at the channel length of 8 µm under the negative bias stress. When the channel length was 10 and 15 µm, Vth shifted negatively about 0.7 and 2.5 V. However, Vth shift did not depend on the channel length under the positive bias stress. Under the negative gate bias stress, the holes might not be accumulated uniformly at the channel. Because the band gap of IGZO is large, the effect of negative gate bias is decreased when the back interface is fixed by source/drain electrode. When the channel length decreases, the amount of accumulated hole decreases and Vth shift decreases.

The role of nitridation of nc-Si dots for improving performance of nc-Si nonvolatile memory

We report a nc-Si nonvolatile memory (NVM) device with nitrided nc-Si dots embedded in a floating gate. LPCVD was used to deposit a layer of nc-Si on the tunnel oxide layer at the pressure of 350mTorr. Subsequently as-deposited nc-Si dots were nitrided at 780°C in NH3 ambient. The role of the nitridation of nc-Si dots for improving performance of nc-Si NVM was investigated. First of all, enlarged memory windows have been observed from nitrided nc-Si NVM compared with that of un-nitrided nc-Si NVM because of the reduction of the surface defect states of nc-Si. Secondly, a faster program speed is achieved because the effective gate bias is increased in nitrided nc-Si NVM. Furthermore, the Si nitride cover layer also acts as a potential barrier which enhanced the memory retention time. The mechanism of improving performance of nitrided nc-Si NVM has been discussed.