Effects Of Soft Errors Research Articles

A method to assess the robustness of cryptographic circuits at the design stage

This paper proposes the use of an FPGA-based fault injection technique, AMUSE, to study the effect of malicious attacks on cryptographic circuits. Originally, AMUSE was devised to analyze the soft error effects (SEU and SET) in digital circuits. However, many of the fault-based attacks used in cryptanalysis produce faults that can be modeled as bit-flip in memory elements or transient pulses in combinational logic, as in faults due to radiation effects. Experimental results provide information that allows the cryptographic circuit designer to detect the weakest areas in order to implement countermeasures at design stage.

An Investigation into Soft Error Detection Efficiency at Operating System Level

Electronic equipment operating in harsh environments such as space is subjected to a range of threats. The most important of these is radiation that gives rise to permanent and transient errors on microelectronic components. The occurrence rate of transient errors is significantly more than permanent errors. The transient errors, or soft errors, emerge in two formats: control flow errors (CFEs) and data errors. Valuable research results have already appeared in literature at hardware and software levels for their alleviation. However, there is the basic assumption behind these works that the operating system is reliable and the focus is on other system levels. In this paper, we investigate the effects of soft errors on the operating system components and compare their vulnerability with that of application level components. Results show that soft errors in operating system components affect both operating system and application level components. Therefore, by providing endurance to operating system level components against soft errors, both operating system and application level components gain tolerance.

Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication

Soft Errors are becoming a major concern for modern computing systems. Memories are one of the elements affected by soft errors, which cause bitflips in some of the cells. A number of techniques such as the use of Error Correction Codes (ECCs), interleaving or scrubbing are utilized to mitigate the effects of soft errors on memories. Content Addressable Memories (CAMs) pose additional challenges, as many of those protection techniques are not applicable to CAMs. In this paper, a novel protection technique for CAMs is proposed, showing a convenient way to tackle false positives and negatives, and quantitatively studying the achieved benefit in reliability.

Analysis of Error Masking and Restoring Properties of Sequential Circuits

Scaling of CMOS technology into nanometric feature sizes has raised concerns for the reliable operation of logic circuits, such as in the presence of soft errors. This paper deals with the analysis of the operation of sequential circuits. As the feedback signals in a sequential circuit can be logically masked by specific combinations of primary inputs, the cumulative effects of soft errors can be eliminated. This phenomenon, referred to as error masking, is related to the presence of so-called restoring inputs and/or the consecutive presence of specific inputs in multiple clock cycles (equivalent to a synchronizing sequence in switching theory). In this paper, error masking is extensively analyzed using the operations of state transition matrices (STMs) and binary decision diagrams (BDDs) of a finite state machine (FSM) model. The characteristics of state transitions with respect to correlations between the restoring inputs and time sequence are mathematically established using STMs; although the applicability of the STM analysis is restricted due to its complexity, the BDD approach is more efficient and scalable for use in the analysis of large circuits. These results are supported by simulations of benchmark circuits and may provide a basis for further devising efficient and robust implementations when designing FSMs.

Memory Reliability Analysis for Multiple Block Effect of Soft Errors

Multiple bit upsets (MBU) are analyzed from the perspective of the number of accessed blocks (NAB) in multiple memory block structures. The NAB represents the number of accessed blocks for a single memory operation. Statistical model of the MBU with regards to the NAB is developed, and its correlation to the test results presented. The tests were performed with neutron irradiation facility at The Svedberg Laboratory. The NAB in structure of multiple memory blocks is one of the most important parameter in determining the reliability of the memory. Although multiple cell upsets can be effectively spread out as multiple single bit upsets by interleaving distance scheme, the word failure rates are increased by combination of multiple events from multiple memory blocks. The proposed model can be effectively used for the estimation of the mean time to the failure with different design parameters during the early design states.

SEU Fault-Injection in VHDL-Based Processors: A Case Study

Evaluating the sensibility of a given circuit with respect to soft errors became a main issue especially if it is intended to operate in space or at high altitudes. A hardware/software (HW/SW) approach to study the effects of soft errors by fault injection in the VHDL model of a CPU (Control Processor Unit) is presented and illustrated by results obtained for a LEON3 processor. The LEON3 is set to execute two benchmark algorithms. The first one is a typical 3x3 matrix multiplication, whereas the second one is a self-converging algorithm which is intended to provide correct results even if a failure occurs in the middle of the execution. The results of fault-injection campaigns targeting the register file unit of the processor are compared to those issued from a state-of-the-art method, the C.E.U. (Code Emulated Upset). One of the main advantages of the proposed method is the larger targeted Single Event Upset (SEU) sensitive area leading to improved error rate predictions.

A Cell Sizing Technique for Mitigating Logic Soft Errors in Gate-level Designs

The effect of logic soft errors on the degradation of the reliability becomes more crucial in the case of nano-meter semiconductor designs. Several hardening techniques have been repor ...

Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection

Estimation of soft error sensitivity is crucial in order to devise optimal mitigation solutions that can satisfy reliability requirements with reduced impact on area, performance, and power consumption. In particular, the estimation of Single Event Transient (SET) effects for complex systems that include a microprocessor is challenging, due to the huge potential number of different faults and effects that must be considered, and the delay-dependent nature of SET effects. In this paper, we propose a multilevel FPGA emulation-based fault injection approach for evaluation of SET effects called AMUSE (Autonomous MUltilevel emulation system for Soft Error evaluation). This approach integrates Gate level and Register-Transfer level models of the circuit under test in a FPGA and is able to switch to the appropriate model as needed during emulation. Fault injection is performed at the Gate level, which provides delay accuracy, while fault propagation across clock cycles is performed at the Register-Transfer level for higher performance. Experimental results demonstrate that AMUSE can emulate soft error effects for complex circuits including microprocessors and memories, considering the real delays of an ASIC technology, and support massive fault injection campaigns, in the order of tens of millions of faults within acceptable time.

An approach to analyze effects of soft errors on program level

Computer hardware components are susceptible to soft errors which could result in incorrect program execution with improvement of semiconductor technology. To measure the reliability of hardware components, it is important to know the effect of soft error on program outcome. This paper analyzes the effects of soft errors on the level of the program. We choose an approach which combines a high level with a low level to model the program. According to the behaviors of soft errors on hardware components during the instruction pipeline, we build a soft error model. Based on our program model and soft error model, the effect of soft errors on the whole computing program is explored from the granularity of the function. Furthermore, data flow errors and control flow errors which are two main implicit program errors caused by soft errors are analyzed respectively. Based on our analyses, we give a method to estimate the Architectural Vulnerability Factor (AVF) of hardware components statically. Our experiments illustrate this method and indicate our analysis results that there are different program behaviors under the effects of soft errors, especially the ability for the program to mask program errors which are caused by soft errors.

Exploration of the effects of soft errors from dynamic software behaviours

Soft errors can affect system reliability by influencing software execution. Dynamic implementation for software-based soft error tolerance methods can protect more types of codes; hence, the method can cover more soft errors. Based on the background of dynamic soft error tolerance, this study proposes an approach to analyse dynamic software behaviours under the effects of soft errors. The authors use a special program model that combines abstract computing on the high level with computing of instructions on the low level. On the high level, programs are divided with the granularity of function. On the low level, every function is implemented by the instructions. Those effects of soft errors on instructions on the low level are passed to the computing results of function on the high level. Backed by the computing results of function on the high level, the caused instruction errors that can lead to incorrect program outcome are distinguished within a function. Based on those different level software behaviours with our program model, the dynamic program reliability model is built under the effects of soft errors. From the dynamic program reliability model, we can see the relationship between the characteristics of dynamic program and reliability of dynamic program under the effects of soft errors. Finally, the experimental results of the authors fault injection experiments validate the dynamic program reliability model. In addition, the experimental results also demonstrate the authors analyses of different dynamic software behaviours under the effects of soft errors.

Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs

This article re-examines the soft error effect caused by radiation-induced particles beyond the deep submicron regime. Considering the impact of process variations, voltage pulse widths of transient faults are found no longer monotonically diminishing after propagation, as they were formerly. As a result, the soft error rates in scaled electronic designs escape traditional static analysis and are seriously underestimated. In this article we formulate the statistical soft error rate (SSER) problem and present two frameworks to cope with the aforementioned sophisticated issues. The table-lookup framework captures the change of transient-fault distributions implicitly by using a Monte-Carlo approach, whereas the SVR-learning framework does the task explicitly by using statistical learning theory. Experimental results show that both frameworks can more accurately estimate SERs than static approaches do. Meanwhile, the SVR-learning framework outperforms the table-lookup framework in both SER accuracy and runtime.

Design Framework for Soft-Error-Resilient Sequential Cells

This paper presents a design framework for soft-error-resilient sequential cells, by introducing a new sequential cell called LEAP-DICE and evaluating it against existing circuit techniques in the “soft error resilience-power-delay-area” design space in an 180 nm CMOS test chip. LEAP-DICE, which employs both circuit and layout techniques, achieved the best soft error performance with a 2,000X improvement over the reference D flip-flop with moderate design costs. This study also discovered new soft error effects related to operating conditions.

An adaptive method to tolerate soft errors in SRAM-based FPGAs

In this paper, we present an adaptive method that is a combination of SEU-avoidance in CAD flow and adaptive redundancy to tolerate soft error effects in SRAM-based FPGAs. This method is based on the modification of T-VPack and VPR tools. Three different steps of these tools are modified for SEU-awareness: (1) clustering, (2) placement and (3) routing. Then we use the unused resources as redundancy. We have investigated the effect of this method on several MCNC benchmarks. This investigation has been performed using three experiments: (1) SEU-awareness in clustering with redundancy, (2) SEU-awareness in clustering and placement with redundancy and (3) SEU-awareness in clustering, placement and routing with redundancy. With a confidence level of 95%, the results show that, using each of these three experiments, the system failure rate of ten MCNC circuits has been decreased between 4.52% and 10.42%, between 10.25% and 21.63%, and between 10.48% and 24.39%, respectively.

Mitigation of soft errors in SRAM-based FPGAs using CAD tools

This paper presents three methods to reduce the system failures resulted from soft errors: (1) an adaptive redundancy-based method that utilizes unused resources to tolerate the effects of soft errors in SRAM-based FPGAs; (2) an SEU-aware method in CAD flow of SRAM-based FPGAs to mitigate the effects of soft errors which is based on T-VPack and VPR tools and functions without any redundancy; and finally, (3) combination of these two methods to realize whether these SEU reduction methods are cumulative or not when they are applied in sequence. The effects of these methods have been investigated on several MCNC benchmarks. The results show that the system failure rate of circuits implemented on FPGAs decreases about 3.59% using the first method, 4.60%, 10.09%, and 12.45% in three cases of the second method, and 7.47%, 15.94%, and 17.43% in three cases of the third method. These results show that the effect of combining the first and the second methods is cumulative.

Static Analysis of Register File Vulnerability

With continuous technology scaling, soft errors are becoming an increasingly important design concern even for earth-bound applications. While compiler approaches have the potential to mitigate the effect of soft errors with minimal runtime overheads, static vulnerability estimation-an essential part of compiler approaches-is lacking due to its inherent complexity. This paper presents a static analysis approach for register file (RF) vulnerability estimation. We decompose the vulnerability of a register into intrinsic and conditional basic-block vulnerabilities. This decomposition allows us to develop a fast, yet reasonably accurate RF vulnerability estimation mechanism. We validate and compare a linear equation based method and an iterative method. Also we demonstrate a practical application of RF vulnerability estimation to compiler optimizations. Our experimental results on benchmarks from MiBench suite indicate that not only our static RF vulnerability estimation is fast and accurate, but also compiler optimizations enabled by our static estimation can achieve very cost-effective protection of register files against soft errors.

Simulated Fault Injection Using Simulator Modification Technique

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms.

Two effective methods to mitigate soft error effects in SRAM-based FPGAs

This paper proposes an effective architecture that can mitigate Single Event Upset (SEU) effects in SRAM-based FPGAs. The architecture employs two different methods in both logic and interconnection resources. The logic resources utilize a new function generator that can tolerate 100% of single faults in its configuration memory while it can generate all the k-input Boolean functions. In the interconnection resources, a kind of formation redundancy that can detect 94% of single faults in its configuration memory is applied. Both methods are based on an interesting relation in Boolean functions, identified as mapping. By this concept, a Boolean function is generated by modifying the inputs of other Boolean functions. The effectiveness of the proposed architecture is procured by a standard fault injection tool; moreover, different parameters such as required area, power, and delay are achieved by using synopsis® synthesis tool. The results show that the area, power, and delay overheads are respectively 179%, 94%, and 60% in comparison with the simple architecture.

On the Usefulness of Detecting Soft Errors in Parallel Pipelines for High-Speed Machine Vision Based on Organic Computing

Computer hardware is always in danger of being hit by ionized particles which cause different kinds of faults. In this paper, the effect of transient soft-errors on the stages of parallel pipelines is investigated by the example of emergent algorithms and machine vision. A fault injection model is introduced and the corresponding protection scheme is presented. During simulation, the number of relevant faults showed to be relatively small and the effect on the pipelines was mostly negligible. However, the costs for protection are low possibly making use of protection worthwhile.

Circuit optimization techniques to mitigate the effects of soft errors in combinational logic

Soft errors in combinational logic circuits are emerging as a significant reliability problem for VLSI designs. Technology scaling trends indicate that the soft error rates (SER) of logic circuits will be dominant factor for future technology generations. SER mitigation in logic can be accomplished by optimizing either the gates inside a logic block or the flipflops present on the block boundaries. We present novel circuit optimization techniques that target these elements separately as well as in unison to reduce the SER of combinational logic circuits. First, we describe the construction of a new class of flip-flop variants that leverage the effect of temporal masking by selectively increasing the length of the latching window thereby preventing faulty transients from being registered. In contrast to previous flip-flop designs that rely on logic duplication and complicated circuit design styles, the new variants are redesigned from the library flip-flop using efficient transistor sizing. We then propose a flip-flop selection method that uses slack information at each primary output node to determine the flip-flop configuration that produces maximum SER savings. Next, we propose a gate sizing algorithm that trades off SER reduction and area overhead. This approach first computes bounds on the maximum achievable SER reduction by resizing a gate. This bound is then used to prune the circuit graph, arriving at a smaller set of candidate gates on which we perform incremental sensitivity computations to determine the gates that are the largest contributors to circuit SER. Third, we propose a unified, co-optimization approach combining flip-flop selection with the gate sizing algorithm. The joint optimization algorithm produces larger SER reductions while incurring smaller circuit overhead than either technique taken in isolation. Experimental results on a variety of benchmarks show average SER reductions of 10.7X with gate sizing, 5.7X with flip-flop assignment, and 30.1X for the combined optimization approach, with no delay penalties and area overheads within 5-6%. The runtimes for the optimization algorithms are on the order of 1-3 minutes.

Soft Errors in SRAM-FPGAs: A Comparison of Two Complementary Approaches

As SRAM-based field-programmable gate arrays (FPGAs) are introduced in safety- or mission-critical applications, the availability of suitable Electronic Design Automation (EDA) tools for predicting systems dependability becomes mandatory for designers. Nowadays designers can opt either for workload-independent EDA tools, which provide information about system's dependability disregarding the workload the system is supposed to elaborate when deployed in the mission, or workload-dependent approaches. In this paper, we compare two tools for predicting the effects of soft errors in circuits implemented using SRAM-based FPGAs, a workload-independent one (STAR) and a workload-dependent one (FLIPPER). Experimental results show that the two tools are complementary and can be used fruitfully for obtaining accurate predictions.