Effects Of Parasitic Parameters Research Articles

Experimental characterization of on-chip inductor and capacitor interconnect: part I. series case

Detailed experimental investigations described here show the overall characteristics of on-chip inductor and capacitor serial interconnects (L--Cs) on silicon substrates. Using a new equivalent circuit model and the measured S parameters obtained by deembedding techniques, we examine and compare a single inductor, single capacitor, and two sets of series L--Cs. Agreement between the measured and simulated S parameters is excellent. At low frequency, the first resonant frequency f/sub res/ of series L--Cs can be easily determined by f/sub res/=(2/spl pi//spl radic/(LC))/sup -1/, while at high frequency, parasitic parameter effects of both the substrate and the metal strips on f/sub res/ of the L--Cs circuit must be considered.

A New Multifunctional Sensor for Measuring Oil/Water Two-phase State in Pipelines

This paper presents a non-contact U form multi-functional sensor for the oil pipeline flow measurement. Totally four thin and narrow copper plates are twined on both sides of the sensor, from which two variables (capacitance, self inductance) are to be examined as the two functional outputs of the sensor. Thus, the liquid concentration (oil and water), temperature are finally evaluated. The flow velocity inside the pipeline could also be estimated by computing the cross correlation of the capacitance-pair. To restrain the effects of parasitic parameters and improve the dynamic response of the sensor, a proper shielding strategy is considered. A suitable algorithm for data reconstruction is also presented in the system design.

On the effect of parasitic parameters on efficiency in energy compression networks

This paper describes and analyzes a generalized approach to compression networks that uses both opening and closing switches. An efficiency of compression equation showing the dependence of efficiency on parasitic parameters is derived. This equation indicates that a unique geometric mean relationship has to be maintained and an optimum number of stages must exist for maximum energy compression.

Common-Mode Noise Generation in a DC-to-DC Converter

Analytical and experimental considerations of the common-mode noise in a dc-to-dc connverterare discussed. Analyzing the mechanism of the common-mode noise generation by means of a high-frequency equivalent circuit, we estimate the output noise voltage generated during the transistor's turn-on time. This commonmode noise consists mainly of two frequency components distributed in several megahertz. The effects of parasitic parameters on the noise voltage and frequencies are clarified. In addition, the effect of a common-mode choke on the noise suppression is discussed experimentally.