Effective Gate Oxide Thickness Research Articles

A design of nanoscale double-gate FET based ring oscillator with improved oscillation frequency using device engineering

In this paper, the performance of inverter and ring oscillator circuits based on the nanoscale double-gate (DG) FET is improved by using device engineering approaches. The modification of the parameters affecting the intrinsic delay time of the DGFET, such as on-current and the total gate capacitance can be improved the oscillation frequency of the ring oscillator. Accordingly, the effects of gate oxide thickness (tox) and body thickness (tbody) on the electrical characteristics of the device and circuit-level have been investigated so that we could provide a design of ring oscillator with improved oscillation frequency. Moreover, the enhanced source doping concentration and graded-channel (GC) techniques have been applied and analyzed at the device-level to ameliorate the oscillation frequency of the ring oscillator. Finally, we have presented the graded-channel (GC) strategy with two types of high-low (HL) and low-high (LH). The extracted results illustrate that the total gate capacitance of the LH-GC-DGFET is improved significantly compared to the HL-GC-DGFET. Consequently, the efficient design of the ring oscillator based on LH-GC-DGFET with superior oscillation frequency is proposed. The TCAD mixed-mode simulation has been used for simulating the circuits.

Hall effect mobility in inversion layer of 4H-SiC MOSFETs with a thermally grown gate oxide

The inversion layer mobility of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with a thermally grown gate oxide was investigated using Hall effect measurements. To clarify the fundamental scattering properties of inversion layer mobility in SiO2/4H-SiC systems, we examined the effects of nitridation treatment after thermal oxidation and the gate oxide thickness on Hall effect mobility (μHall) in the inversion layer of 4H-SiC MOSFETs. The effect of nitridation treatment after thermal oxidation on phonon-limited mobility (μphonon) was investigated by using a p-type well region with an epitaxial layer with extremely low acceptor concentration (NA). It was found that nitridation treatment had little effect on μphonon for gate oxide thicknesses of 5 nm and 50 nm. The carrier transport properties were experimentally evaluated from the viewpoint of the effects of gate oxide thickness and nitridation treatment after thermal oxidation. Here, we used samples with a moderate NA of 1 × 1016 cm−3, which enabled us to distinguish μphonon, Coulomb-limited mobility (μCoulomb) and surface roughness-limited mobility (μSR). It was found that thermally grown SiO2/4H-SiC systems have the common feature that the dominant scattering components in the inversion layer are phonon scattering and Coulomb scattering and not surface roughness scattering at room temperature within the measured effective normal field (Eeff).

Effect of eccentricity on junction and junctionless based silicon nanowire and silicon nanotube FETs

In this paper, the effect of eccentricity on Junction-based Silicon Nanowire FET, Junction-based Silicon Nanotube FET, Junctionless-based Silicon Nanowire FET, and Junctionless-based Silicon Nanotube FET is investigated. Three kinds of eccentric structures are considered here. The impact of eccentricity on effective gate oxide thickness thereby gate oxide capacitance, and effective channel width are studied using 3D numerical simulations. Average radius of an ellipse is used to generate a model which captures the impact of eccentricity on gate oxide capacitance, and verified using TCAD simulations in MOS nanowire structure. The impact of eccentricity on ON current (ION), OFF current (IOFF), ION/IOFF ratio, and Unity gain cutoff frequency are investigated. Eccentricity increases the effective gate oxide thickness, the effective channel width, ION, and IOFF but reduces ION/IOFF ratio.

A Novel Approach to Analysis of F-N Tunneling Characteristics in MOS Capacitor Having Oxide Thickness Fluctuation

The new indicators, effective gate oxide thickness tc and effective gate electrode area D, and their combination are applied for a new analysis method of Fowler-Nordheim (F-N) tunneling characteristics in MOS capacitor having oxide thickness fluctuation. This method considering the conduction properties of F-N tunneling characteristics correlates its characteristics to the oxide reliability. These indicators quantified with the influence of the oxide thickness fluctuation can provide the net values of the electric field and the current density on the gate oxide. This new analysis method will lead to reducing the evaluation time for the reliability assessment.

III–V tri-gate quantum well MOSFET: Quantum ballistic simulation study for 10 nm technology and beyond

In this work, quantum ballistic simulation study of a III–V tri-gate MOSFET has been presented. At the same time, effects of device parameter variation on ballistic, subthreshold and short channel performance is observed and presented. The ballistic simulation result has also been used to observe the electrostatic performance and Capacitance–Voltage characteristics of the device. With constant urge to keep in pace with Moore’s law as well as aggressive scaling and device operation reaching near ballistic limit, a full quantum transport study at 10nm gate length is necessary. Our simulation reveals an increase in device drain current with increasing channel cross-section. However short channel performance and subthreshold performance get degraded with channel cross-section increment. Increasing device cross-section lowers threshold voltage of the device. The effect of gate oxide thickness on ballistic device performance is also observed. Increase in top gate oxide thickness affects device performance only upto a certain value. The thickness of the top gate oxide however shows no apparent effect on device threshold voltage. The ballistic simulation study has been further used to extract ballistic injection velocity of the carrier and ballistic carrier mobility in the channel. The effect of device dimension and gate oxide thickness on ballistic velocity and effective carrier mobility is also presented.

A 2D Transconductance and Sub-threshold behavior model for triple material surrounding gate (TMSG) MOSFETs

A 2D analytical model for transconductance, Sub-threshold current and Sub-threshold swing for Triple Material Surrounding Gate MOSFET (TMSG) is presented in this paper. Based on the solution of two dimensional Poisson equation, the physics based model of sub-threshold current of the device is derived. The model also includes the effect of gate oxide thickness and silicon thickness on the sub-threshold swing characteristics. Transconductance to drain current ratio of the triple material surrounding gate is calculated since it is a better criterion to access the performance of the device. The effectiveness of TMSG design was scrutinized by comparing with other triple material and dual material gate structures. Moreover the effect of technology parameter variations is also studied and proposed. This proposed model offers basic guidance for design of TMSG MOSFETs. The results of the analytical model are compared with the MEDICI simulation results thus providing validity of the proposed model.

Modeling and simulation of carbon nanotube-semiconductor heterojunction vertical field effect transistors

The scaling behavior of carbon nanotube (CNT)-organic semiconductor heterojunction enabled vertical field effect transistors are comprehensively examined by two-dimensional consistent device simulations. Tunneling current is modeled by introducing tunneling induced carrier generation into the current continuity equation. Modulation of both the CNT-semiconductor Shottky barrier height and thickness are examined. The tunneling current and thermionic current dominate at on-state and off-state, respectively. Barrier height modulation plays an important role and improves the on-off current ratio and sub-threshold swing considerably. Small diameter CNT is preferred for enhancing the gate control on the CNT-channel barrier height. Reducing the effective gate oxide thickness by either a thin oxide or a high-κ gate insulator gives improvement of device performance, but the former one works more efficiently. The channel length and CNT spacing should be carefully engineered due to the trade-off between device characteristics in the sub-threshold and above-threshold region.

Statistical Timing and Power Optimization of Architecture and Device for FPGAs

Process variation in nanometer technology is becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, we first develop closed-form models of chip-level FPGA leakage and timing variations. Experiments show that the mean and standard deviation computed by our models are within 3% from those computed by Monte Carlo simulation. We also observe that the leakage and timing variations can be up to 3X and 1.9X, respectively. We then derive analytical yield models considering both leakage and timing variations, and use such models to evaluate the performance of FPGA device and architecture considering process variations. Compared to the baseline, which uses the VPR architecture and device setup based on the ITRS roadmap, device and architecture tuning improves leakage yield by 10.4%, timing yield by 5.7%, and leakage and timing combined yield by 9.4%. We also observe that LUT size of 4 gives the highest leakage yield, LUT size of 7 gives the highest timing yield, but LUT size of 5 achieves the maximum leakage and timing combined yield. To the best of our knowledge, this is the first in-depth study on FPGA architecture and device coevaluation considering process variation.

Degradation of High-$k$/Metal Gate nMOSFETs Under ESD-Like Stress in a 32-nm Technology

The degradation of nMOSFETs induced by nondestructive electrostatic discharge-like (ESD-like) stress in a 32-nm bulk CMOS technology was studied using I- V characteristics and charge pumping measurements. The impact of stress on drain saturation current (Idsat), threshold voltage (Vt), transconductance peak (gm), and subthreshold swing (SS) is reported. For ESD stress applied on the drain, little degradation was observed until the device failed by drain-to-source filamentation. In contrast, for stress applied on the gate, positive ESD-like stress decreases Idsat and increases Vt of the nMOSFETs significantly, and the degradation increases with the effective gate oxide thickness. Different from positive bias temperature instability (PBTI) stress, the Vt shift depends on temperature rather weakly, which indicates a new dominant charge-trapping mechanism on the time scale of ESD events. In addition to the degradation of Vt and Idsat, the positive stress also caused significant damage to the Si/oxide interface in the nMOSFETs with thick gate oxide. The degradation of Idsat, Vt , gm, and SS under positive stress is more severe for devices with high-k gate compared to devices with SiON gate. It is also shown that the degradation induced by negative ESD-like stress applied on the gate is much smaller compared to positive stress. Finally, the impacts of the stress on the gate leakage current and on the the subsequent PBTI degradation kinetics are also studied.

High-voltage DMOS integrated circuits using floating-gate protection technique

An efficient low power protection scheme for thin gate oxide of high voltage (HV) DMOS transistor is presented. To prevent gate-oxide breakdown and protect HV transistor, the voltage controlling its gate must be within 5 V from the HV supply. Thus signals from the low voltage domain must be level shifted to control the gate of this transistor. Usually this level shifting involves complex circuits that reduce the speed besides requiring of large power and area. In this paper, a simple and efficient protection technique for gate-oxide breakdown is achieved by connecting a capacitor divider structure to the floating-gate node of HV transistor to increase its effective gate oxide thickness. Several HV circuits, including: positive and negative HV doublers and level-up shifters suitable for ultrasound sensing systems are built successfully around the proposed technique. These circuits were implemented with 0.8 μm CMOS/DMOS HV DALSA process. Simulation and experimental results prove the good functionality of the designed HV circuits using the proposed protection technique for voltages up to 200 V.

Threshold voltage modelling and gate oxide thickness effect on polycrystalline silicon thin-film transistors

This paper presents an analytical model for calculating the threshold voltage in polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with large grains. In the present study, it is assumed that the oxide-silicon interface traps are uniformly distributed and the channel of the device contains only a single grain boundary. Further, the effect of gate oxide thickness on threshold voltage and hence on transfer characteristics has also been incorporated in this paper. It is observed that scaling down of the oxide thickness is an efficient way to reduce the threshold voltage and hence to improve the poly-Si TFT characteristics at different temperatures and trap densities. The results so obtained are compared with the available experimental data which show a satisfactory match thus justifying the validity of the model.

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

Parametric Failures Can Be a Pain in the Backside

Abstract Parametric failures are of two general types. One type is due to defects that affect circuit parameters. The other type, which occurs in defect-free parts, is the result of interdie parameter statistical variation. IC failures can be caused by variations in any number of parameters including Leff, Weff, IDsat, Vt, contact resistance, effective gate oxide thickness, source and drain resistance, interconnect sheet resistance, and intrametal spacing affecting cross-talk, ground bounce noise, and IR voltage drops. These failures often influence the maximum operating frequency of the IC and are seldom detected by simple stuck-at fault, delay fault, functional, or IDDQ tests. This article discusses the origin, classification, and detection of a wide range of parametric failures.

Current Drive Improvement Using Enhanced Body Effect Factor Due to Finite Inversion Layer Thickness in Variable-Threshold-Voltage Complementary MOS (VTCMOS)

A new scheme for recovering the current drive that is degraded due to the finite inversion layer thickness and gate depletion, using a high-speed mode variable-threshold-voltage complementary metal oxide semiconductor (VTCMOS), has been proposed. This scheme utilizes the body effect. The effects of finite inversion layer thickness and gate depletion enhance the body effect, and therefore substrate bias works more effectively. This enhancement of body effect is experimentally examined by measuring fully depleted silicon-on-insulator (FD SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). The effect of gate oxide thickness, the scalability of this scheme, and the impact of the short-channel effect are also discussed.

Numerical simulation of quantum effects in high-k gate dielectric MOS structures using quantum mechanical models

In this paper the electrical characteristics of metal oxide semiconductor (MOS) capacitors with high-k gate dielectric are investigated with quantum mechanical models. Both the self-consistent Schrodinger–Poisson (SP) model and the density gradient (DG) model are solved simultaneously to study quantum confinement effects (QCEs) for MOS capacitors. A computationally efficient parallel eigenvalue solution algorithm and a robust monotone iterative (MI) finite volume (FV) scheme for the SP and DG models are systematically proposed and successfully implemented on a Linux cluster, respectively. With the developed simulator, we can extract the effective gate oxide thickness from capacitance voltage (C-V) measurements for TaN and Al gate NMOS capacitors with Zr O2 and Si O2 gate dielectric materials. We found that quantization effects of 5.0 nm Zr O2 MOS samples cannot be directly equivalent to commonly quoted effects of 1.5 nm Si O2 MOS samples. Achieved benchmarks are also included to demonstrate excellent performances of the proposed computational techniques.  2002 Elsevier Science B.V. All rights reserved.

Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures

The charge retention characteristics in scaled SONOS nonvolatile memory devices with an effective gate oxide thickness of 94 Å and a tunnel oxide of 15 Å are investigated in a temperature range from room temperature to 175°C. Electron charge decay rate is sensitive to the temperature, whereas hole charge decay rate remains essentially constant. Based on experimental observations and an amphoteric trap model for nitride traps, an analytical model for charge retention of the excess electron state is developed. Using this thermal activated electron retention model, the trap distribution in energy within the nitride film is extracted.

Reliability considerations in scaled SONOS nonvolatile memory devices

The memory characteristics and reliability of a SONOS nonvolatile memory device are determined, to a large extent, by the charge transport and trapping properties of its storage nitride film. In this paper we investigate carrier trapping phenomenon in a scaled SONOS transistor with an effective gate oxide thickness of 94 and a nitride storage layer deposited with LPCVD at 680°C. Atomic Force Microscopy (AFM) has been employed to examine the surface quality of deposited nitride films. We have found that nitride film deposited at 680°C shows the lowest surface roughness, as compared to the films formed at 725C and 650°C. With a charge separation technique, we have demonstrated that the charge centroid is deep into the nitride layer at low injection levels and moves towards the center of the film as the injection level is increased. From our measurement, a trap density of 1.7×10 19 cm −3 in the nitride has been determined. Devices with nitride (2.1 Å RMS roughness) deposited at 680°C show less degradation in data retention with respect to erase/write cycling when compared to devices with nitride (2.9 Å RMS roughness) deposited at 725°C.

Effects of Inversion Layer Quantization and Polysilicon Gate Depletion on Tunneling Current of Ultra-Thin SiO2 Gate Material

ABSTRACTWe have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

Impact of oxide thickness on SEGR failure in vertical power MOSFETs; development of a semi-empirical expression

This paper investigates the role that the gate oxide thickness (T/sub ox/) plays on the gate and drain failure threshold voltages required to induce the onset of single-event gate rupture (SEGR). The impact of gate oxide thickness on SEGR is experimentally determined from vertical power metal-oxide semiconductor field-effect transistors (MOSFETs) having identical process and design parameters, except for the gate oxide thickness. Power MOSFETs from five variants were specially fabricated with nominal gate oxide thicknesses of 30, 50, 70, 100, and 150 nm. Devices from each variant were characterized to mono-energetic ion beams of Nickel, Bromine, Iodine, and Gold. Employing different bias conditions, failure thresholds for the onset of SEGR were determined for each oxide thickness. Applying these experimental test results, a previously published empirical expression is extended to include the effects of gate oxide thickness. In addition, observations of ion angle, temperature, cell geometry, channel conductivity, and curvature at high drain voltages are briefly discussed.

Threshold voltage model for deep-submicrometer MOSFETs

The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>