Electrostatic Discharge Events Research Articles

Electrostatic discharge failure and protection of single-walled carbon nanotube field-effect transistors

Abstract Carbon nanotube based field effect transistors (CNT-FETs) have been considered as a preferred alternative to the traditional Si-based MOSFETs. Here we investigated the electrostatic discharge (ESD) failure characteristics of single-walled CNT (SWCNT) FET. In ESD event, the instantaneous high current will generate an amount of heat in the CNT-FET channel resulting in its thermal failure owing to its randomly aligned SWCNT networks. The CNT-FET failure mechanism and its ESD characteristics with various key parameters are studied in detail. These insights provide new ideas and a guidance for the research and application of CNT-FETs. In order to achieve a full chip ESD protection network for CNT chips, we referred to commonly used ESD devices in silicon-based processes and designed CNT based ESD devices, including GD-CNT-FET (Gated-VDD CNT-FET) and RC-CNT-FET (RC trigger CNT-FET). CNT-FET with randomly aligned SWCNT networks, whose failure current level is only about 50µA/µm, needs larger areas to achieve effective ESD protection.

On-board equipment testing procedure for the effects of electrostatic discharges

On-board equipment testing procedure for the effects of electrostatic discharges

Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission

Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission

Incident beam current impact on space-charge retention in electron dynamitron irradiated polymethyl methacrylate

Dielectric charging aboard spacecraft and satellites is a persistent and pressing issue in materials design and applications. This study investigated the effect of electron irradiation on charge trapping and leakage properties in polymethyl methacrylate, which is necessary for determining the maximum permissible fluence of radiation before the material is pushed beyond its breakdown threshold in charged particle radiation-intense environments. It was observed that dielectric breakdown in the form of an electrostatic discharge event cannot be induced under the conditions of this experiment after an amount of time that is dependent on initial electron fluence. This time limit for which an electrostatic discharge can be induced was found to be longer for the lower beam current irradiations. The work presented here discusses the factors affecting charge leakage using a global electric field-driven model.

Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit

Electrostatic discharge (ESD) and electromigration are critical issues that significantly impact the reliability of ICs. While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention, potentially compromising IC reliability. This work analyzes various types of metal with different lengths, widths, and angles commonly used in ESD protection circuits in the CMOS process. The objective is to observe their behavior under continuous ESD zapping. The ESD-induced electromigration of metallization in the CMOS process has been analyzed, and metal sensitivity to system-level ESD events has also been identified. It is also analyzed from the perspective of energy that the ESD energy that metal can withstand will decrease as the ESD voltage increases, which will be even more detrimental to the ESD reliability of ICs. The findings from this study aim to provide valuable insights for designing metal lines in ICs to enhance ESD protection.

Electrostatic discharge impacts on the main shaft bearings of wind turbines

Abstract. This paper studies the electrostatic discharge effect in wind turbines, a possible trigger source of the main bearing current. A lab setup with a charge generator and downsized wind turbine was built to verify the impact of electrostatic discharge on the main bearing current. In the test, a fatal amplitude for the bearing current was found at only −93 mV driven voltage on the shaft. Compared with the bearing current driven by the common-mode voltage, the electrostatic discharge effect triggers the bearing breakdown at a lower shaft voltage but much higher bearing current amplitude. The results demonstrate that the electrostatic discharge effect is a pattern of the bearing current in wind turbines and is much more dangerous to the bearing.

ESD Events to Wearable Medical Devices in Healthcare Environments—Part 1: Current Measurements

Wearable medical devices are widely used for monitoring and treatment of patients. Electrostatic discharge can render these devices unreliable and cause a temporary or permanent disturbance in their operation. In a healthcare environment, severe electrostatic discharge (ESD) can occur while a patient, lying down or sitting on a hospital bed with a wearable device, discharges the device via a grounded bedframe. To protect the devices from ESD damage, the worst-case discharge conditions in the usage environment need to be identified. Previous studies by authors revealed that such events could be more severe than the conventional human metal model (HMM). However, the impact of various body postures and device location on the body and the severity of the discharge current compared with HMM have not been investigated for healthcare environments. This study is an attempt to address the gap in the literature by investigating severe discharges in such environments and characterizing their current waveforms for three postures (standing on the floor, sitting, and lying down on a hospital bed), two device locations (hand and waist), and four body voltages (2, 4, 6, and 8 kV). This study highlights that the IEC 61000-4-2 standard may not be sufficient for testing wearable medical devices.

A Simple Method for Determining Shallow Charge Distributions in Dielectrics via Pulsed Electroacoustic Measurements

The understanding of charge dynamics in dielectric materials is paramount in mitigating electrostatic discharge events for spacecraft. The most critical spacecraft charging events are found to result from incident electrons in the energy range of 10 keV to 50 keV. The charge embedded in dielectric materials in this energy range are deposited a distance into the material on the order of a few to tens of microns. One way to measure and understand the deposited charge is via pulsed electroacoustic measurements (PEA). However, the typical PEA spatial resolution of ~ 10 μm is not sufficient to resolve or discern charge deposited at the lower end of this incident electron energy range, where deposited charge distributions are obscured by the superposition of the signal originating from induced mirror charge on the electrode of the pulsed electroacoustic system. A simple method is proposed and demonstrated in which reference measurements from a pristine sample are used to separate the effect of the induced mirror charge from the measured embedded charge to obtain a more accurate determination of the deposited charge distribution.

Electromagnetic Fields Radiated by Electrostatic Discharges: A Review of the Available Approaches

Electrostatic discharge (ESD) is a physical phenomenon that may destroy electronic components due to its high discharge current that may reach a few amperes in just a few ns. However, another major aspect of ESD is the related high-frequency electromagnetic (E/M) fields radiated by the ESD event. The electronic equipment that is affected by the ESD phenomenon is additionally affected by the induced voltages caused by these E/M fields. This is the reason that the current version of the IEC 61000-4-2 on ESD has a special reference to these fields and the measurement setup. Starting with the classical formulation of these fields, this paper reviews the most popular techniques for calculating the ESD electromagnetic fields while also emphasizing the best methods for minimizing computational effort. There is also a separate section for the measurement techniques that have been applied in research works, whose outcomes could be implemented in the next revision of the IEC 61000-4-2. It is extremely important for the next revision to include these measurement setups and the E/M field sensors because the ESD generators should comply with certain values related to the E/M fields they produce.

Effect of Electrostatic Discharge (ESD) on Heat Response Performance of NiCr Micro-heater

The NiCr micro-heater is a key element of MEMS-based electro-explosive device (mEED), while electrostatic discharge (ESD) may excite the micro-heater accidentally. To discover mechanism that how the ESD excitations effect on heat response performance of NiCr micro-heater, electro-thermal conversion process was numerically modelled by using commercial software. Three different shapes of micro-heaters, including rectangular, V-shape and square ones, are designed, and a series of simulation models are built under ESD events of 25kV, 5000Ω, 500pF and 25kV, 500Ω, 150pF. Heat response performance of NiCr micro-heater with different shapes and sizes were numerically computed under the said ESD events and compared with. The critical safety value at which LTNR and copper azide would not be ignited accidentally were calculated according to the fitted formulas. Conclusions are that maximum temperature decreases exponentially with increase of width of rectangular micro-heater, decreases exponentially with increase of wm and α of V-shape micro-heater, and decreases exponentially with increase of length or width of square micro-heater. The ESD event of 25kV, 500Ω, 150pF is a more severe case for micro-heater than ESD event of 25kV, 5000Ω, 500pF. These results could supply critical data to guide the design of MEMS -based EED for ESD protection.

A False Trigger-Strengthened and Area-Saving Power-Rail Clamp Circuit with High ESD Performance.

A power clamp circuit, which has good immunity to false trigger under fast power-on conditions with a 20 ns rising edge, is proposed in this paper. The proposed circuit has a separate detection component and an on-time control component which enable it to distinguish between electrostatic discharge (ESD) events and fast power-on events. As opposed to other on-time control techniques, instead of large resistors or capacitors, which can cause a large occupation of the layout area, we use a capacitive voltage-biased p-channel MOSFET in the on-time control part of the proposed circuit. The capacitive voltage-biased p-channel MOSFET is in the saturation region after the ESD event is detected, which can serve as a large equivalent resistance (~106 Ω) in the structure. The proposed power clamp circuit offers several advantages compared to the traditional circuit, such as having at least 70% area savings in the trigger circuit area (30% area savings in the whole circuit area), supporting a power supply ramp time as fast as 20 ns, dissipating the ESD energy more cleanly with little residual charge, and recovering faster from false triggers. The rail clamp circuit also offers robust performance in an industry-standard PVT (process, voltage, and temperature) space and has been verified by the simulation results. Showing good performance of human body model (HBM) endurance and high immunity to false trigger, the proposed power clamp circuit has great potential for application in ESD protection.

Overview about E-Mobility Conducted Immunity Tests on ESA Communication Lines

Due to the complexity of the Automotive Electromagnetic Compatibility legislation in force, this article aims to describe a simplified overview of several technical standards relating to conducted immunity tests on electronic sub-assemblies, where communication lines are involved. The discussed automotive standards reported in this article are: ISO 11452-1 and ISO 11452-4 for continuous narrowband electromagnetic fields immunity test, bulk current injection and tubular wave coupler, IEC 61000-4-5 for immunity against surge events, IEC 61000-4-4 for electrical fast transient/burst events immunity, ISO 10605 for electrostatic discharge events immunity, ISO 7637-2 and ISO 7637-3 for transient disturbances events immunity. For each cited standard, disturbance bandwidth evaluation was performed. Practical examples are reported, with analysis and discussion of some of the adoptable disturbance countermeasures applicable on controlled area network communication lines, and possible design advantages and disadvantages with different types of filtering and suppression circuit solutions.

Analysis of Electrostatic Discharge Interference Effects on Small Unmanned Vehicle Handling Systems

Electrostatic discharge is a common phenomenon in daily life, and the electromagnetic pulse radiation generated during discharge can cause great harm to power, communication, sensing, and other equipment, resulting in systems not working properly. To verify the safety and reliability of unmanned vehicle handling systems in complex electromagnetic environments, the interference effect of electrostatic discharge, a common source of electromagnetic interference in life, on unmanned vehicle systems was studied. According to the electrostatic discharge interference mechanism, typical electrostatic discharge mode, and discharge model, an unmanned vehicle handling system was tested for electrostatic discharge according to the ISO10605-2008 standard. Based on the measured data, the effect of electrostatic discharge on the safety and functionality of the unmanned vehicle handling system and its sensors was analyzed, and threshold values for the failure of the unmanned vehicle handling system under different discharge methods, discharge models, and discharge polarity were obtained. When the electrostatic discharge voltage amplitude is only 2 kV, the vehicle’s LiDAR data sensor cannot work normally due to the echo reception circuit, and the failure rate of LiDAR continues to increase with increasing discharge voltage. When the discharge voltage is only 4 kV, the millimeter-wave radar is disconnected from the vehicle module due to the electrostatic discharge interference of the transmission cable, and when the discharge voltage is 12 kV, the unmanned vehicle is unable to provide stable and accurate environmental information to avoid collisions. This study provides a reference for the design of electromagnetic protection of unmanned equipment and will have a guiding role in enhancing the construction of reliable, safe, and intelligent equipment in complex electromagnetic environments.

Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors

The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.

ESD-Event Detector for ESD Control Applications in Semiconductor Manufacturing Factories

An electrostatic discharge (ESD)-event detector has been designed and fabricated in a single chip to detect and alarm the ESD events in semiconductor or integrated circuit (IC) manufacturing environments. The experiment measured results showed that the peak-to-peak voltage of the detected signal during an ESD event has a strong correlation with its ESD-stress voltage level. <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">The proposed ESD-event detector can determine a</b> detected <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">signal to be an ESD pulse if its signal amplitude is higher than the settable threshold and its duration time is under 500 ns.</b> The ESD-event detector circuit, including a <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">450 MHz</b> logarithmic amplifier, a comparator, and a time discriminator, has been implemented in a single chip with a total silicon area of only 693 × 563 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\mathbf{m}}^2$</tex-math></inline-formula> and fabricated by 0.18- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m CMOS process. <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">The detector can detect high-frequency transient signals up to 450 MHz, which has been successfully verified in the field tests by detecting the signals generated from the ESD generators, the human-body model tester, and the field-induced charged-device model tester.</b> The proposed ESD-event detector can efficiently perform the real-time ESD monitoring applications in the IC and semiconductor manufacturing factories.

Editorial Introduction to the Special Issue on Electrostatic Discharge and Immunity—From IC to System

The papers in this special issue focus on scientific contributions in the field of electrostatic discharge (ESD) and immunity—from integrated circuits (ICs) to system. ESD can damage or disrupt electronic systems. With continued scaling of ICs, a combined approach of IC and system forms the best path for understanding and ensuring robustness. This relates to the IC itself: input/output (I/O) structures, power distribution network (PDN), interfaces between IP blocks, as well as the interaction of external protection devices with internal ESD protection structures during system level stress. To effectively protect the ICs fabricated in the advanced nanoscale CMOS processes, the turn-on speed of ESD protection devices must be enhanced to quickly discharge ESD current before the internal circuits are damaged by ESD stresses. Not only component level ESD events, the system level ESD test specified in the IEC 61000-4-2 standard has been used to verify ESD immunity of the microelectronics products. During system level ESD testing, the ESD problems relates to soft failures. So far, only few models for soft failures have been reported. It becomes visible that well designed hard failure protection can also reduce the likelihood of soft failures as most of the current is diverted from the IC and will not disturb the PDN of the IC. ESD robustness in the system level and component level are both important to meet the electromagnetic compatibility (EMC) regulations and/or standards in the industry.

Research progress on electrostatic discharge law of aircraft and radiation signal detection technology

At present, the number of combat aircraft in China is huge and in a stage of rapid development, and the electrostatic discharge effect of aircraft during flight has become one of the important issues related to the reliability and safety of aircraft; At the same time, the use of electrostatic discharge radiation signals to achieve aircraft detection and positioning is also an urgent need to develop an effective means of dealing with stealth technology, with significant advantages and broad prospects for military applications. In this paper, from the aspects of the harm of electrostatic discharge to aircraft, the characteristics and radiation laws of electrostatic discharge of aircraft, and the detection technology of electrostatic signal of aircraft, this paper expounds the research progress at home and abroad, analyzes the new problems faced by the electrostatic discharge effect of aircraft and static detection technology, and looks forward to the next research and development direction. The analysis results show that the research hotspots of aircraft electrostatic discharge effect and static detection technology focus on the new mechanism of electrostatic discharge and new radiation signal detection technology brought about by new materials, new environments, new loads and new requirements, and the work that needs to be focused on urgent research mainly includes the study of the integrated characteristics of multi-source electrostatic discharge of aircraft, the long-distance detection of electrostatic discharge information, and the evaluation method of the effect of electrostatic discharge on the airborne electronic system, etc., which provide technical support for improving the reliability and safety of aircraft during flight.

Experimental Study on the Space Electrostatic Discharge Effect and the Single Event Effect of SRAM Devices for Satellites

Space Electrostatic Discharge Effect (SESD) and Single Event Effect (SEE) are two major space environmental factors that cause spacecraft failure. Previous studies have established that both can lead to soft errors such as upset of memory cells. An ESD generator and a pulsed laser experimental facility were used to test a low-power asynchronous timing monolithic SRAM. The characteristics of soft error number, single/multi-bit upsets, and supply current values were compared for similarities and differences. The test revealed that SEE-induced soft errors were mainly single-bit upsets (SBU), whereas SESD-induced soft errors were predominantly multi-bit upsets (MBU). Additionally, when soft errors occur in the circuits, the current of the power supply drops, which enables the device to be evaluated by monitoring the current value. This study provides experimental support for distinguishing device errors caused by these two effects, as well as references for further accurate identification of in-orbit faults and corresponding protection design.

Seesaw-type modulation of secondary electron emission characteristics of polytetrafluoroethylene-MgO composite coating

The electrostatic discharge (ESD) from polymer insulators is one of the environment-related anomalies on spacecraft. Theoretically, to mitigate the ESD effects, we could modulate the secondary electron yield (SEY, σ) close to 1 in the entire energy range, suppressing surface charges. However, no single polymer insulator has been reported to achieve this seesaw-type modulation of SEY. Here, we exploringly designed and prepared MgO particles doped polytetrafluoroethylene (PTFE) composite coating to achieve this goal, which exhibits not only the reduced SEY characteristic of the microstructured PTFE coating at low energy but also the enhanced SEY characteristic of the double-layer structure of PTFE and MgO at high energy. The simulation and experiment results demonstrate that MgO particles doped PTFE coating achieves this seesaw-type modulation of SEY. The optimal MgO concentration is 20%, where the maximum SEY (σmax) changes from 2.0 to 1.1; the SEY at 10 keV (σ10k) changes from 0.6 to 0.8, and the higher energy of the SEY equal to 1 (Ep2) increases from 4.5 to 6.5 keV. The discharge test of the microstrip antennas with PTFE-MgO composite coating in a scanning electron microscope verifies the role of the seesaw-type SEY modulation in surface charge suppression. This study supplies an essential reference for suppressing surface charges on vacuum electronics based on modulation of secondary electron emission characteristics.

Unique Rise Time Sensitivity Leading to Air Discharge System-Level ESD Failures in Bidirectional High Voltage SCRs

This article discloses a unique failure mode in high-voltage bidirectional (Bi-Di) silicon-controlled rectifier (BDSCR) cells during International Electrotechnical Commission (IEC) air discharge electrostatic discharge (ESD) events. Failure was found to be sensitive to IEC measurement conditions or variabilities such as the speed of IEC gun and angle of approach, which causes different stress rise times. Hence, observed failure was a peculiar function of the rise times of the discharge current waveform. Remarkably, failure in high-voltage BDSCR was observed only for a window of current rise times. A new approach is presented using 3-D TCAD simulations of multifinger BDSCR to study and probe the failure mechanism dependent on these system-level stress parameters and variabilities. By emulating the experimental conditions in a 3-D TCAD environment, physical insights are developed to probe the root cause of the observed air discharge failures. Furthermore, a device engineering approach has been proposed, with the help of 3-D TCAD simulations of multifinger BDSCR, which computationally demonstrated improved robustness of BDSCR multifinger cells against IEC air discharge failures. The proposed design mitigates the nonuniform turn-on and failure due to IEC stress or rise time variability at the cost of a negligibly small area overhead.