Effect Of Bias Temperature Stress Research Articles

Bias temperature stress induced hydrogen depassivation from Al2O3/InGaAs interface defects

We study the reliability of Al2O3/InGaAs metal-oxide-semiconductor gate stacks by investigating the effect of bias temperature stress on the charge trap density at the Al2O3/InGaAs interface and in the bulk oxide. Under extended negative biasing at 100 °C, the gate stacks display a notable increase in the interface trap density (Dit), but little change in the border trap density. This phenomenon is more prominent for samples exposed to a H2/N2 forming gas anneal (FGA) than for the as-deposited samples. Negative gate bias applied during 100 °C thermal stress negates the FGA-induced passivation of interface states and causes convergence of the Dit of the post-FGA and as-deposited gate stacks with increasing biasing time. This appears to be caused by hydrogen depassivation of interface traps under bias temperature stress, which is further supported by an observed hydrogen isotope effect when comparing the rate of Dit increase after annealing in hydrogenated versus deuterated forming gas. A N2 anneal control experiment also indicates that the stability of the interface trap density of post-FGA Al2O3/InGaAs gate stacks is more strongly influenced by the behavior of hydrogen at the interface than by the thermal treatment effect of the anneal.

Effect of Bias Temperature Stress on the Anti-Reflection HfO2 Layer in Complementary Metal Oxide Semiconductor Image Sensors

The effects of various electrical characteristics of HfO2 in CMOS image sensors on bias-thermal stress instability were evaluated. In this work, the HfO2 dielectric layer was used as the anti-reflection layer of image sensors because it had negative charges and could electrically form a p+ layer on a silicon photodiode surface. After the HfO2 layer was stressed with electric field 0.5 MV/cm, 200 °C, and 10 min, there was severe electrical degradation such as +18.8 V flatband voltage shift. In order to investigate this degradation, the oxide trap charges and border trap charges of the HfO2 layer were measured and calculated. Based on these results, the interface trap density and minority carrier generation lifetime, which are directly related to the dark current in CMOS image sensors, were measured. The interface trap density degraded from 4.5×1011 to 1.0×1012 cm-1 eV-1 and the generation lifetime also degraded from 983 to 17 µs after stress application. This trap generated degradation model is suggested for CMOS image sensors. Therefore, pre-stabilization of bias-thermal stress should be implemented to use the HfO2 layer in modern CMOS image sensors.

Erratum to: The effect of bias-temperature stress on Na+ incorporation into thin insulating films

Erratum to: The effect of bias-temperature stress on Na+ incorporation into thin insulating films

The effect of bias-temperature stress on Na+ incorporation into thin insulating films

The action of Na(+) incorporation into thin insulating films and transport therein under influence of a bias voltage and temperature (BT stress) is the subject of this work. Deposited onto highly n-doped Si wafers, the insulators get BT stressed and subsequently investigated by means of time-of-flight-secondary ion mass spectrometry (ToF-SIMS). A thin PMMA film, spin-coated onto the insulator, serves as host matrix for a defined amount of Na(+), provided via sodium triflate. Combining BT stress and ToF-SIMS depth profiling enables the unambiguous detection of Na(+), incorporated into the insulating material. The insulators of interest vary in their nitride content: SiO(2), SiO(x)N(y), and Si(3)N(4). For SiO(2), it is shown that once a threshold BT stress is exceeded, Na(+) gets quantitatively incorporated from PMMA into the underlying insulator, finally accumulating at the SiO(2)/Si interface. A quantitative assessment by combination of Butler-Volmer kinetics with hopping dynamics reveals activation energies of E(a) = 1.55 - 2.04 eV for Na(+) transport in SiO(2) with varying thickness. On the other hand, SiO(x)N(y) and Si(3)N(4) films show a different Na(+) incorporation characteristic in this type of experiment, which can be explained by the higher coordination of nitrogen and hence the reduced Na(+) permeability within these insulators.

Bias temperature instability from gate charge characteristics investigations in N-Channel Power MOSFET

This paper reports the effects of bias temperature stress (positive and negative bias temperature instabilites, PBTI–NBTI) on threshold voltage, input capacitance and Miller capacitance of N-Channel Power MOSFET. The device is stressed with gate voltage under precision temperature forcing system. The bias temperature cycling also induces instabilities N-Channel Power MOSFET. The gate charge characteristics have been investigated before and after stress. The capacitances (the drain–gate and drain–source capacitances) are shifted due to the degradation of device physical properties under different stress time and stress temperature conditions. Bi-dimensional simulations have been performed for the 2D Power MOSFET structure and accurately analyzed. Gate charge characteristics of the device have been correlated to physical properties to analyze mechanisms responsible of parameter degradations. It is shown that the main degradation issues in the Si Power MOSFET are the charge trapping and the trap creation at the interface of the gate dielectric performed by energetic free carriers, which have sufficient energy to cross the Si–SiO2 barrier.

TCS study of n- and p-channel amorphous silicon thin-film transistors

We apply a transient current spectroscopy (TCS) to n-channel and, for the first time, also to p-channel TFTs made with a-Si:H and a-SiN x :H. The data are analysed in terms of an effective density of interface states, N i (E). We find that N i (E) has a maximum near midgap and a minimum in each half of the band gap, the lower one being less pronounced than the upper one. The TFT properties are modified by exposing the nitride to an oxygen plasma prior to the deposition of the a-Si:H film. Short exposures (t e 2 as a gate insulator. We also study the effect of bias-temperature stress (BTS) on the properties of our TFTs. Positive (negative) BTS causes a metastable increase of N i (E) predominantly in the lower (upper) half of the band gap. Our results suggest that the metastable defects but not the stable ones are caused by chemical equilibration within a defect pool.