Edge Direct Tunneling Research Articles

Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes

Extending double-gate FinFET scaling to sub-10nm technology regime requires device-engineering techniques for countering the rise of direct source to drain tunneling (DSDT), edge direct tunneling (EDT) and short channel effects (SCE) that degrade FinFET I-V characteristics. Symmetric underlap is effective for eliminating EDT, diminishing DSDT, and lowering the fringe component of gate capacitance. However, excessive symmetric underlap also lowers the on-current, which is mainly due to thermionic emission. In this work, it is demonstrated that at sub-10nm node, asymmetric underlapped FinFETs with slightly longer underlap toward drain side than source side are superior to symmetric underlapped FinFETs due to further improvement in I on /I off and reduction in gate-to-drain capacitance. Using quantum mechanical device simulations, FinFETs with various degrees of underlap have been analyzed for improvement in I-V characteristics. A FinFET model for circuit simulations has been constructed that captures the major sub-10nm leakage components, namely, thermionic emission, DSDT, EDT, direct gate oxide tunneling and its associated components. By simulating a 10-stage NAND circuit and a LEON3 processor with interconnect parasitics using these devices, it is shown that asymmetric underlap instead of symmetric underlap in sub-10nm FinFETs can offer lower energy consumption with improved performance for near-threshold logic and higher energy-efficiency for super-threshold logic operation.

Characterization of Edge Fringing Effect on the $C$ –$V$ Responses From Depletion to Deep Depletion of MOS(p) Capacitors With Ultrathin Oxide and High-$\kappa$ Dielectric

The edge fringing effect (EFE) on the capacitance-voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> ) responses from depletion to deep depletion (DD) of p-substrate metal-oxide-semiconductor capacitors with ultrathin oxide (2.1-2.9 nm) and high-κ dielectric was examined. It was found that the EFE plays a significant role on the initiation voltage of DD in the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> curve. The shape of capacitance in DD has been characterized in detail via a modified quantum-mechanical-based EFE model with the consideration of edge direct tunneling current conduction concept. Excellent agreement between the model and the experimental data for gate oxide has been achieved. To elucidate the enhanced fringing effect at edge, the effective surface field ratio between edge and bulk was adopted to clarify the role of injected carriers with the EFE mechanism. It was found that the extracted ratio increases with the oxide thickness and the initiation voltage of DD accordingly.

Investigation of Gate Etch Damage at Metal/High-$k$ Gate Dielectric Stack Through Random Telegraph Noise in Gate Edge Direct Tunneling Current

Plasma damage on a high-k/SiO2 dielectric at a gate edge during a dry etch process is investigated. The damage was observed to generate slow oxide traps, causing a random telegraph noise (RTN) in a gate edge direct tunneling current. Through the analysis of the RTN, the distribution of the oxide traps in the high-k/SiO2 dielectric was obtained, and the plasma-damage-induced oxide traps were found to be distributed over a wide area of the high-k/SiO2 sidewall at the gate edge region.

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlNx) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlNx) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.

Investigation of Random Telegraph Noise in Gate-Induced Drain Leakage and Gate Edge Direct Tunneling Currents of High-$k$ MOSFETs

Random telegraph noise (RTN) in gate-induced drain leakage (GIDL) and gate edge direct tunneling (EDT) leakage currents under GIDL bias conditions were characterized in MOSFETs with a high-k gate dielectric for the first time. The RTNs were analyzed through systematic measurement and calculation. The results indicate that a high-current state in a GIDL current can be attributed to electron capture due to thermal emission. However, electron emission from a trap was mainly affected by gate bias. Both capture and emission times in the RTN of the EDT current had gate bias dependence. Moreover, multilevel RTN waveforms were detected in a device, and our analysis indicated that the multilevel RTN is the result of the combination of the RTNs of the GIDL and EDT currents. The analysis also indicated that two independent traps in the high- k gate dielectric can produce a four-level RTN in the GIDL current. This paper provides the fundamental physics required to understand such leakages in nanoscale MOSFETs and devices that utilize band-to-band tunneling.

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

The degradation of device under GIDL (gate-induced drain leakage current) stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC (stress induced leakage current) in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.

Electrical Measurement of Local Stress and Lateral Diffusion Near Source/Drain Extension Corner of Uniaxially Stressed n-MOSFETs

On a 1.27-nm gate oxide n-MOSFET that undergoes longitudinal stress via a layout technique, subthreshold current is measured as a function of the gate edge to shallow-trench isolation (STI) spacing and is transformed via bandgap shift into the source/drain extension corner stress. The extracted local stress is quantitatively comparable with those of the channel as created by the gate direct tunneling measurement in inversion, the mobility measurement, and the threshold voltage measurement. In addition, its dependencies on the gate edge to STI spacing confirm the validity of the layout technique in controlling the corner or channel stress. The gate edge direct tunneling (EDT) measurement in accumulation straightforwardly leads to the quantified gate- to-source/drain-extension overlap length. Particularly, a retarded diffusion length of 1.1 nm for a stress change of -320 MPa and the resulting strain-induced activation energy both are in satisfactory agreement with those of the process simulation. A physically oriented analytic model is, therefore, reached, expressing the lateral diffusion as a function of the corner stress.

Edge direct tunneling current in nano‐scale MOSFET with high‐Kdielectrics

Purpose – Choosing suitable high‐K gate dielectrics to reduce the off‐state leakage (Ioff) by edge direct tunneling mechanism, demonstrating that the decreased Ioff increase significantly when the gate dielectrics permittivity are above 25. The purpose of this paper is to report that HfSiON and HfLaO are promising gate dielectrics.Design/methodology/approach – The off‐state gate current, drain current, and substrate current are investigated. The Id‐Vgs characteristics for the 50 and 90 nm NMOSFET with various gate dielectrics are studied. Edge direct tunneling current (IEDT) with various gate dielectrics including SiO2, Si3N4 and HfO2 are compared and this paper also examines the IEDT with HfSiON and HfLaO gate dielectrics.Findings – IEDT prevails over conventional gate‐induced drain‐leakage current (IGIDL), subthreshold leakage current (ISUB), band‐to‐band tunneling current (IBTBT) and it dominates off‐state leakage current. A large increase in off‐state leakage current occurs for smaller devices due to ...

A quantitative study of the relationship between the oxide charge trapping over the drain extension and the off-state drain leakage current

In this letter, we report an approach to quantitative study of the relationship between the oxide charge trapping over the drain extension due to electrical stress and the off-state drain leakage current. It is found that positive charge trapping over the drain extension leads to a significant increase in the off-state drain current if the edge direct tunneling (EDT) is dominant in the drain current but in contrast, it leads to a reduction in the drain current if the band-to-band tunneling in the Si surface is dominant. A quantitative relationship between the charge trapping and the off-state drain leakage current in the EDT regime is established. From the measurement of the off-state current in the EDT regime, the charge trapping can be determined by using the approach developed in this study.

Two-Dimensional Self-Consistent Calculation of Gate Direct Tunneling Current in Metal–Oxide–Semiconductor Transistors

The gate direct tunneling current in sub-100-nm n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) in inversion regime has been calculated by solving the one-dimensional Schrödinger equations and two-dimensional (2D) Poisson equation self-consistently. This is the first 2D calculation of gate tunneling currents, although the model is not fully 2D. In the model, the wave-function penetration into the gate oxide and gate electrode is taken into account. The 2D effects of the gate tunneling current, in particular due to the edge direct tunneling (EDT) of electrons from the source and drain extensions, are investigated in detail. For lower gate voltages, the EDT current becomes a dominant component in the total gate current and exceeds the channel-to-gate current by three orders of magnitude at the maximum. Due to the EDT, the gate current is considerably dependent on the doping concentration and the gate overlapped length of the source and drain extensions.

Study on Nano Complementary Metal Oxide Semiconductor Gate Leakage Current

This work examines different components of the leakage current in scaled N and P-metal oxide semiconductor field-effect transistor (MOSFET) with ultra thin gate oxide. Experimental results show that the gate tunneling leakage current through the source/drain extension region (also named edge direct tunneling, EDT) is the largest component, which dominates the maximum off-state power consumption of a nano-scaled transistor. To clarify the relationship between this largest leakage component and the size of the source/drain to gate overlap region, the proposed capacitance–ratio method (C–R method) was used to precisely extract the dimensions of the source/drain to gate overlap, Lov. To reduce the gate-tunneling leakage at the source/drain edge, a modified gate dielectric structure is proposed and verified in this work.

On–off switching of edge direct tunneling currents in metal-oxide-semiconductor field-effect transistors

On–off switching behaviors or two-level random telegraph signals (RTS) are measured in the low voltage (−1.40 V&amp;lt;VG&amp;lt;−0.88 V) edge direct tunneling currents in ultrathin gate stack (10 Å oxide+10 Å nitride) n-channel metal-oxide-semiconductor field-effect transistors. The plausible origin is the process-induced defects in terms of localized gate stack thinning (or equivalently the conductive filament). In such extrinsic case, the current trapping–detrapping theories can adequately elucidate the data, particularly the RTS magnitude as large as 18%. The current–voltage characteristic associated with a certain defective spot is assessed straightforwardly, showing remarkable compatibility with existing oxide thinning case. Systematic measurements of RTS in the terminal currents allow for determining the occurrence probability as well as locations of defects, and may be treated as a sensitive process monitor.

Polyreoxidation process step for suppressing edge direct tunneling through ultrathin gate oxides in NMOSFETs

In this work, we identify polyreoxidation as a process step for selectively thickening the gate oxide at the edges (in the gate overlap region), and hence for suppressing the edge component of direct tunneling through ultrathin gate oxides in NMOSFETs. It is shown that by varying the different polyreoxidation parameters viz: temperature and polyreoxidation time it is possible to achieve different levels of gate oxide edge thickening. This essentially implies that a desired level of gate leakage current may be maintained without modifying the gate oxidation process significantly.

Edge hole direct tunneling leakage in ultrathin gate oxide p-channel MOSFETs

This paper examines the edge direct tunneling (EDT) of holes from p/sup +/ polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness T/sub OX/=1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field E/sub OX/ at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates E/sub OX/ to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once E/sub OX/ is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected.

Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs

This paper examines the edge direct tunneling (EDT) of electron from n/sup +/ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs having ultrathin gate oxide thicknesses (1.4-2.4 nm). It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT) and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field E/sub OX/ at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates E/sub OX/ to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension. Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.

Impact of gate direct tunneling current on circuit performance: a simulation study

The influence of gate direct tunneling current on ultrathin gate oxide MOS (1.1 nm/spl les/t/sub ox/spl les//1.5 nm, L/sub g/=50-70 nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low V/sub dd/ static-logic circuits. However, dynamic logic and analog circuits are more significantly influenced by the off-state leakage current for oxide thickness below 1.5 nm, under low-voltage operation. Based on the study, the oxide thicknesses which ensure the International Technological Roadmap for Semiconductors (ITRS) gate leakage limit are outlined both for high-performance and low-power devices.