Impact of gate direct tunneling current on circuit performance: a simulation study

Abstract

The influence of gate direct tunneling current on ultrathin gate oxide MOS (1.1 nm/spl les/t/sub ox/spl les//1.5 nm, L/sub g/=50-70 nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low V/sub dd/ static-logic circuits. However, dynamic logic and analog circuits are more significantly influenced by the off-state leakage current for oxide thickness below 1.5 nm, under low-voltage operation. Based on the study, the oxide thicknesses which ensure the International Technological Roadmap for Semiconductors (ITRS) gate leakage limit are outlined both for high-performance and low-power devices.