E-beam Testing Research Articles

Studying of in-vessel component materials under high power electron beam and steady-state plasma loads

Combined tests of tungsten mock-ups with thermocyclic test in the electron beam facility with the load up to 50 MW/m² and subsequent irradiation with steady-state plasma load up to 1 MW/m² in PLM device have been carried out to simulate a material degradation under loads expected in a fusion reactor. Cracks of 1–5 microns and more have been formed on the surface of the tungsten during e-beam test. Melted layer observed in the area of e-beam hot spot load. Plasma load led to a formation of nanostructured layers on the surface.

Electrical testing for failure analysis: E-beam testing

Electrical testing for failure analysis: E-beam testing

Nuclear microprobe analysis and imaging: Current state of the art performances

The current state-of-the-art performances claimed for nuclear microbeam spatial resolutions are: (a) 400 nm spot sizes for high current (100 pA) proton beams, (b) 400 nm for high current alpha particle beams, (c) 100 nm for low proton current (<0.1 pA) applications such as Scanning Transmission Ion Microscopy (STIM) and Ion Beam Induced Charge (IBIC) and (d) 50 nm for low current alpha particles. These claims, however, have been undermined not only by the lack of a common and generally accepted resolution standard, but also by the lack of a consistent approach between groups regarding a recognised method of beam spot measurement. The lack of a definitive method for assessing spatial resolution is hindering the future development of nuclear microprobes to higher spatial resolutions. We require the manufacture of resolution standards specifically tailored for nuclear microprobe spot size measurements, for both high and low current operations. Until such resolution standards are available, one commercially available standard which has high potential for high current proton beam resolution tests is the Ebeam test chip manufactured for the characterisation of electron beam testers. This chip has patterns as small as 0.5 μm in size produced in 0.5 μm thick aluminium by direct electron beam writing. Using both analytical Particle Induced X-ray Emission (PIXE) imaging and PIXE line scans, the nuclear microscope facility at the National University of Singapore has demonstrated spatial resolutions of less than 400 nm for a 100 pA beam of 2 MeV protons. Low current resolution standards have more stringent requirements. One potential standard tested in Singapore is a prototype self-supporting X-ray mask used in X-ray lithography. This test standard, however, is not commercially available at the moment, is fragile and therefore difficult to handle and easily fractured. Using off-axis STIM imaging and line scanning over this mask, the NUS nuclear microscope facility has demonstrated beam spot sizes less than 130 nm for a 1 pA 2 MeV proton beam.

Examination of material performance of W exposed to high heat load: Postmortem analysis of W exposed to TEXTOR plasma and E-beam test stand

Examination of material performance of W exposed to high heat load: Postmortem analysis of W exposed to TEXTOR plasma and E-beam test stand

Examination of material performance of W exposed to high heat load: Postmortem analysis of W exposed to TEXTOR plasma and E-beam test stand

We have examined the behavior of high Z limiters exposed to TEXTOR edge plasma and found that under certain conditions high Z materials are compatible with plasmas. In high density Ohmic plasmas the accumulation of a high Z impurity in the plasma center with significant radiation is observed, whereas an auxiliary heating like NBI and ICRH enhances the impurity exhaust with saw tooth activity. For a practical use of high Z plasma facing materials, extremely high heat load from the plasma becomes a serious concern. In the present work we have conducted the high heat load tests of tungsten (W) using two different heat sources, one is the W limiter exposed to TEXTOR plasma and the other is various W samples heat loaded with an intense E-beam using the JEBIS facility in Japan Atomic Energy Research Institute (JAERI). From the test results we have to conclude that W, if applied in the form of the bulk material, should be used above the ductile brittle transition temperature (DBTT) but below about 1500°C to avoid the recrystallization. Maximum heat load tolerable without surface melting is about 20 MW/m 2 for several seconds. The monocrystalline used at high temperatures shows very good performance, though the production of the monocrystalline with a desired shape is not easy. Considering its brittle nature, hard machining and heavy mass, bulk W cannot be a structure material but be used as a thin tile or deposited film on some structure materials. Unfortunately, however, the thermal expansion coefficient of W is so small that brazing of W to a heat sink material like Cu which has a much larger thermal expansion coefficient would easily result in cracking due to the large thermal stress. Thus the development of tungsten plasma facing component (PFC) needs much effort in future.

Turn-on speed of grounded gate nMOS ESD protection transistors

The turn-on speed of nMOS transistors (nMOST) is of paramount importance for robust Charged Device Model (CDM) protection circuitry. In this paper the nMOST turn-on time has been measured for the first time in the sub-halve nanosecond range with a commercial e-beam tester. The method may be used to improve CDM-ESD hardness by investigating the CDM pulse responses within circuit. Furthermore it is shown that the CDM results of various protection layouts can be simulated with a SPICE model.

The limits of automatic systems for defect location using e-beam testing

A lot of development and research has been done in order to make the e-beam analysis automatic. However, in the case of the defect location on ICs whose internal structure is unknown, automatic methods are generally not efficient. In this paper, based on a real example of defect location through e-beam testing, we show that in cases of poor information, an efficient (i.e. quick and cheap) method cannot be fully automated: is has to use the experience of the analyst and must include some advanced external tests so as to reduce the number of e-beam observations.

High performance field-emission column for next generation E-Beam Tester

Electron beam testing is a state-of-the-art method for design verification and failure analysis of highly integrated devices. The progressive development in IC complexity and performance, however, is forcing a rapid evolution in electron beam testing technology. The instrumentation required for the next generation of devices must be capable of probing lines with geometries under half a micrometer with GHz signals applied. In accordance with these needs, a new E-Beam Tester has been developed. By applying field emission technology to electron probe generation, a remarkable increase in performance has been obtained by comparison with conventional systems. An extremely high beam current is focused to a probe of 50 nm diameter. With this precise signal measurements with 10 GHz bandwidth can be performed, such as delay measurements with a time resolution of better than 10 ps. The measurement voltage accuracy of low amplitude signals in the mV-range also benefits from the improved probe performance.

Low aberration in-lens analyzer for e-beam tester using collimation by both magnetic and electrostatic lenses

We have explored ways to reduce aberration in lens collimation (LC)-type in-lens analyzers for e-beam testers used to probe submicon interconnections of LSI's. To reduce the chromatic aberration, the magnetic field distribution width is reduced, shortening its focal length. Also, a new magnetic and electrostatic lens collimation (MELC) analyzer was devised to ensure a voltage measurement accuracy of 0.3 V for interconnections with 0.5 μm line and space. A beam diameter of 0.15 μm was also achieved at a current of 1 nA.

Primary beam address error reduction in E-Beam testing of packaged integrated circuits

Abstract Primary beam address error (or mispositioning) is an undesired effect in E-beam testing, and becomes critical when submicron metal line voltages have to be measured. In order to show that the IC package electrode voltages and output pad currents are the source of a large contribution to the address error, calculations and experimental results on the effect of the electric field are reported. The electrodes, bonding wires and pads effect on the beam mispositioning is calculated by means of a 2-dimensional model. Because of the relative sizes, the error produced by the external electrodes is much larger than that of the pads or wiring bonds. Experimental results agree well with calculations. In order to reduce this undesired effect inherent in E-beam testing, logic isolation of input and/or output pads is proposed. This procedure eliminates large surface voltage and current transitions, improving the beam positioning accuracy.

Electron beam testing: A comparative study of irradiation effects on 54HCUO4 with passivation, without passivation, and with an ultra-thin carbon layer

Irradiation damages caused by low energy electron beam (1 KeV) might occur on testing integrated circuit by Electron beam tester (EBEAM tester). Usually, this effects can be revealed on MOS device by a threshold voltage shift. We present a case study on a bilayer Si3N4/SiO2 passivated circuit 54HCUO4. We made experiment plans on passivated device, on passivation removed devices and on anti-charge-up layer covered devices. Significant threshold voltage shifts were only observed on circuits with passivation removed. These shifts depend on the total dose D and also on the dose rate : at low dose rate we don't observe shifts. Other experiments on oxyniture and an SiO2 passivation layer would confirm the link between irradiation damage, total dose, dose rate and the nature of the passivation.

Sample preparation for electron beam testing: An electrical characterization method to obtain an optimized anti-charge-up carbon layer

Abstract In order to limit positive charge build up in the passivation layer of integrated circuit scanned by low energy electron beam tester (E-BEAM tester), we deposit an ultra thin carbon layer on the device. The thickness of this layer must be weaker than the secondary electron escape depth (voltage contrast) but large enough to ensure sufficient conductivity to evacuate the charge that builds up. Unfortunately, the good thickness depends on circuits, evaporating systems and so on. We present an electrical characterization method based on the measure of the standby current. At the begining of the carbon layer growing, this current slowly rises. After, it sharply increases and finally it proportionally augments as the thickness. From an anti-charge up point of view, the best possible thickness is the end of the standby current skyrocketting. With this method, we obtain an optimized thickness for each circuit.

Pattern matching for automated E-beam testing

Pattern matching between the LSI mask layout database and SEM image is essential for automated e-beam testing. Techniques for calibrating wiring width, compensating for layer misalignment, and generating template images taking into account the effect of passivation films have been developed. We combined these techniques with projection edge extraction correlation (PEC) and had registered wiring probed automatically. Positioning time, which includes stage movement, SEM image acquisition, and pattern matching, was less than 20 s. Positioning accuracy (3σ) was 0.19 μm for metal and 0.55 μm for passivated wiring of an IC with a 2-μm minimum wiring width.

Generation of inherently periodical test patterns for the e-beam test of scan-based designs

Abstract Due to reliability and economic aspects, fault diagnosis comes up to be an essential aid for manufacturing highly integrated circuits. Electron beam testing is a common technique for fault diagnosis purposes. It allows the observation of voltages at internal circuit nodes. If measurements with high voltage and time resolutions are requested and large circuits have to be investigated, long measurement times have to be accepted or measurements are even impossible. Up to now no software tools have been presented which support high resolution measurements with the electron beam test. Considering scan-based circuit designs, this paper describes a new concept and the generation of inherently periodical test patterns leading to a reduction of electron beam test measurement times. Our approach meets hardware difficulties with applying state-of-the-art test pattern generation. Computational results show that a drastic reduction of measurement times can be obtained by applying inherently periodical test patterns. Reduction factors for ISCAS benchmark circuits range between 4 and 255. Therefore, high resolution measurements can be carried out in reasonable times.

Experimental test of high-resolution process modelling in electron beam lithography at 25 to 50 keV

An additive process using the three-level resist scheme for X-ray mask fabrication by electron beam lithography is analysed by Monte Carlo simulation of electron scattering. The resist exposure is calculated for specific e-beam test patterns aimed at 0.2μm resolution. The time evolution of the developed resist profiles is simulated by using a string model for dissolution. Relevant process variables such as e-beam energy (25 to 50 keV) and resist thickness are investigated. Simulation results demonstrate that 50 keV is altogether a preferred condition, compared to 25 keV, leading however to different pattern transfer techniques, according to resist thickness. The process modelling is compared with previously reported experimental results. Good qualitative agreement is found, indicating that modelling can be used as an effective aid in the quantitative evaluation of the process.

FACE: A failure analysis and characterization environment for E-beam testing

VLSI circuits diagnosis demands a test environment with high automation degree. The FACE project has been defined for failure analysis and IC characterization with an electron beam test system. The purpose of this paper is to present Dynamic Fault Probing, one of the analysis methods of FACE, a tool for automatic waveform measurement and comparison. This requires the combination of probe fine positioning and waveform processing techniques, which insures the optimized acquisition, automatic processing and comparison of the signals.

E-beam test system with higher performance by improving signal source : Takaaki Numajiroet al. Proceedings of the 21st Symposium on Reliability and Maintainability, Japan, 121 (June 1991)

E-beam test system with higher performance by improving signal source : Takaaki Numajiroet al. Proceedings of the 21st Symposium on Reliability and Maintainability, Japan, 121 (June 1991)

Test method in voltage contrast mode using liquid crystals

This paper deals with the use of liquid crystals to visualize the internal electrical behavior of VLSI circuits. The complexity of present VLSI chips requires powerful tools to detect possible defects. For such a purpose, internal contactless testing methods have been developed, such as, electron beam or laser testing, to help identify the precise localization of the electrical defect. The aim of this paper is to describe the liquid crystals test method, used at the IBM COMPEC laboratory for failure analysis, in the localization of defects in an integrated circuit. The electro-optical properties of these materials depend on the electric fields present on the chip surface, thus it has become possible to visualize the path information and to determine the areas where the signal is present. Depending on the applied electric field direction, the molecules can rotate if the E value is higher than a threshold value (0.1 V/μm). The liquid crystal testing apparatus is principally equipped with a laser scan microscope, a word generator which emulates the chip, an image processing station and the equipment necessary for the preparation of the samples. For this test method we have two possible applications: the imaging mode, in order to visualize the presence of the signal on the chip surface, and the probing mode, to determine the temporal evolution of the electric signal in one node of the circuit up to a maximum value of 300 KHz, and to discriminate IC logical levels, up to a maximum value of 3 MHz. The great advantage in the use of the SC ∗ liquid crystals, more than the color, is the response time performance of such a phase. SC ∗ can have a switching time of about 1 μs compared with 1 ms for N. In the future the SA phase will allow a response time better than 100 ns. The advantages of such methods are the production of colored pictures, the use of optical microscopy, testing can be done at atmospheric conditions, the ease of set-up and manipulation and finally the low cost of the equipment used. In the failure analysis laboratory it could represent another alternative to the voltage contrast usually performed with E-beam testing. Moreover the possibility of making a measurement in one node of the circuit in order to obtain the internal signal seems very promising. Some examples with memory products will be discussed.

Multipurpose e-beam system for microelectronic structure testing

A relatively cheap system comprising features of conventional SEM, through-lens detection and e-beam tester is presented. Control of data acquisition, processing and presentation is performed by the IBM PC AT/286 computer in standard configuration. The system is designed for use in laboratories for microelectronic research.

Bridging the gap between conventional and E-beam testing

The key to testing is good controllability and good observability of the device under test. Both conditions must be satisfied at the same time. This simultaneity is a major reason why testing is generally difficult. Electron beam testing eliminates the observability problem to a large extent. On the other hand, controllability is becoming more difficult. This is due to the need of periodic signals in the sampling mode, which is considered the predominant mode in electron beam testing. In this paper a survey of the similarities and differences of conventional and electron beam testing is given. The basic features of measures for design for testability are discussed along with their implications for electron beam testing. The need for design modifications and new software tools which support electron beam testing will be made obvious. Most of the conclusions on electron beam testing hold for other methods of contactless testing as well.