E-beam Inspection Research Articles

Novel Control Method and Applications for Negative Mode E-Beam Inspection

Novel Control Method and Applications for Negative Mode E-Beam Inspection

RIE-Induced VIA Defect Inspection Using In-line Voltage Contrast Technique – 0.18 µm Technology

Optical inspection is used in large-scale manufacturing processes to identify the pattern defect. However, the capture rate of killer defects is low due to the resolution limit of optical inspection. The Voltage Contrast (VC) technique of Scanning Electron Microscope (SEM) was developed to detect killer defects. The VC electron beam inspection is a widely used method in the IC manufacturing industry for the monitoring and characterisation of electrical defects at an early stage. The major drawback of E-Beam inspection is low throughput. To enhance the chip yield, some defects should be detected and reduced in the early stage of fabrication. Herein, we present the Back End of Line (BEOL) fabrication with 0.18 µm process technology and the application of VC methodology to inspect electrical defects. The defects mostly occur due to marginal process window, which affects the etching and lithography process. These effects lead to metal shorts and partial etch of interconnect producing open VIA12. Using inline VC-SEM the invisible defects can be detected at an early stage and chip yield can be further improved.

Trainable die-to-database for large field of view e-beam inspection

Extreme ultraviolet lithography has advanced microfabrication of semiconductor devices toward the sub-10-nm generation. In this situation, stochastic defects increase and hence process evaluation requires an entire wafer inspection at high speed. To satisfy this requirement, a large field of view (FoV) inspection with low-resolution enables us to inspect an entire wafer within an acceptable time because the throughput of e-beam inspection depends on imaging resolution. However, low-resolution images are difficult to inspect at high precision using conventional methods because of a smaller photographed defect size and worse signal-to-noise ratio. Moreover, deformation caused by the manufacturing process and larger distortion caused by large FoV result in false detections when we apply die-to-database (D2DB) inspection. To solve these issues, we propose trainable D2DB inspection, which predicts a pixel-value distribution of normal images from a corresponding design layout. The proposed method is robust to low-resolution images because it considers noise and acceptable deformation as variance of the learned distribution. In addition, by introducing a model to predict a misalignment between a design layout and inspection image, trainable D2DB becomes robust to image distortion. Experiments show that trainable D2DB can perform high-precision inspection on images with large noise and image distortion.

Nondestructive Detection of Buried and Latent Defects by Negative Mode E-Beam Inspection

This publication describes the detection of buried defects in 3D NAND flash. It will first explain and motivate the use of negative mode voltage contrast electron beam inspection and then present recent use cases. Negative mode is able to generate a higher electrical field compared to conventional positive mode. A first use case shows that this high field can damage devices during inspection. Careful recipe development is necessary to find the correct dose that allows detection without damaging the device. In the second use case the electric breakthrough is necessary to detect certain defects. Although not electrically active, they are a reliability risk and therefore detection is very important for process improvement. Negative mode electron beam inspection must be used to activate and detect these defects. The higher electrical field, sufficient to break through the damaged insulator makes the defects electrically active and detectable. It also makes the defects visible to electrical test, which is not the case when positive mode inspection is used. Further investigation shows that the breakthrough in this case activates only pre-existing defects and does not affect healthy devices.

Plasma-based area selective deposition for extreme ultraviolet resist defectivity reduction and process window improvement

Extreme ultraviolet (EUV) lithography has overcome significant challenges to become an essential enabler to the logic scaling roadmap. However, it remains limited by stochastically driven defects, such as line breaks and line bridges for aggressive pitches. This is especially relevant for the back end of line, which requires the most aggressive scaling. Stochastic defects reduce device yield and may push device manufacturers to move to EUV multipatterning beyond 36 nm pitch single exposure, which is a costly option. While the lithography and patterning stack can be optimized to provide the largest process window with the lowest number of defects, process margins decrease as smaller pitches are required. Currently, for some lithography stacks, especially spin-on glass based trilayer stacks, the defect-free process window beyond 36 nm pitch is limited by line collapse. Reduction in resist thickness may mitigate pattern collapse, but it may also increase the number of line breaks—trading one killer defect for another. In this paper, we expand on an area selective deposition (ASD) process in situ of an etch chamber to selectively deposit material on the EUV photoresist prior to transferring the pattern downstream. We demonstrate mitigation of resist line notching and breaks while maintaining deposition-free open areas and clear alignment marks. Due to the inherent chemical selectivity of the deposition process as opposed to a purely aspect ratio driven deposition process, thinner resists that, with a normal etch condition would result in line breaks, can now be considered. This drives down flopover defect issues seen with thicker EUV resists and enables several underlayer systems that could otherwise not be considered. Finally, we demonstrate that defectivity levels measured by e-beam inspection post lithography and post pattern transfer and yield are both improved at 30 nm pitch when this ASD process is used.

Wafer Defect Inspection Optimization: Models, Analysis and Algorithms

The prevalence of electronic devices has propelled the tremendous growth of the semiconductor industry in the past half century. The manufacturing of semiconductor wafers is a long and delicate process, where defect points may occur and cause the failure of the entire circuit. As more advanced devices introduce tiny and harder-to-detect defects, improvements in wafer defect inspection technologies are highly desired by the industry. One promising direction is to optimize the positioning of inspection regions for the e-beam inspection tool, so as to cover all suspect defect points on a target area of a wafer while maximizing the throughput of the scan. To this end, we formulate this defect inspection optimization problem (DIOP) as a mixed integer linear programming (MILP) model, and enhance the formulation using variable reduction. To address the computational challenge of solving large-scale DIOP instances, we further propose three approximation methods with theoretical bounds, namely, a constant-factor approximation algorithm that provides heuristic solutions quickly, a polynomial-time approximation scheme (PTAS) that has a strong performance guarantee, and an MILP-based hybrid method that combines the PTAS framework and MILP formulation and is suitable for parallel computing by design. Numerical experiments on synthetic and industry instances show the efficiency and effectiveness of the proposed methods. Particularly, for large-scale instances, the hybrid algorithm is capable of generating near-optimal solutions with theoretical guarantees within practically acceptable computational time.

Stochastic printing failures in extreme ultraviolet lithography

Stochastic effects in lithography are known to be the cause of critical dimension (CD) variability, quantified, e.g., by linewidth roughness or local CD uniformity, but—when the CDs are small—they can also lead to printing failures, and hence have a significant impact on yield. We will focus on these printing failures and review three important topics in this relatively new field. First, we will look at how these failures can be detected and show how either CD-SEM, e-beam inspection, and optical defect inspection can play a useful role. Next, we consider the important question of how the stochastic failure probability (which we quantify by a metric we call “Not OK,” abbreviated NOK) depends on the lithography- and process-settings, a question that is of obvious importance when looking for conditions that will minimize the failure probability and hence maximize the yield. Finally, we will discuss to what extent we can fit experimentally observed failure probabilities, to empirical models. Such models can play a vital role in future OPC-verification flows, where screening full mask layouts for “stochastic hot spots” is expected to become a mandatory step.

Detection of Printable EUV Mask Absorber Defects and Defect Adders by Full Chip Optical Inspection of EUV Patterned Wafers

The ability to rapidly detect both printable EUV mask adder defects as well as mask absorber defects across the entire mask image field is a key enabler for EUV lithography. Current optical wafer-based inspection techniques are only capable of detecting repeater defects on a die-to-die basis for chiplets within the image field. Larger server-type chips that encompass the entire mask image field cannot rely on such a scheme, since the presence of the defect in every die prevents their detection. In this paper, a prototype optical wafer defect inspection methodology designed to detect repeater defects over the entire image field, termed die-to-baseline reference die (D2BRD), is investigated. The sensitivity of this inspection technique is demonstrated and compared to eBeam inspection over a range of defect sizes for both opaque and clear type mask absorber programmed defects. Moreover, the D2BRD methodology is used to monitor printing defect adders present in a lithographic defect test mask, as well as 7-nm BEOL layers. Using defect repeater analysis, SEM review and patch image classification of full chip wafer inspections over several mask cycles, the D2BRD scheme is shown to allow the unambiguous identification of mask adder defects, while suppressing random process defects. This methodology has the potential to define the risk assessment of mask adder defects in the absence of an EUV pellicle, and can play an integral part of the wafer print protection strategy.

The Benefits of High Landing Energy for E-Beam Inspection

E-beam inspection has become one of the most important tools for rapid yield ramp in the semiconductor industry, due to its ability to detect a wide range of defects in-line soon after their formation. This role expansion is due to the increasing difficulty in detecting defects in-line with other traditional methods as well as the continuing evolution of e-beam capability. In the last five years, the role of e-beam inspection has expanded from detection of electrically active, buried defects using voltage contrast inspection to also detection of many challenging physical defect types as well as systematic patterning defects. This paper reports on the impact of an important recent improvement in e-beam inspection tool capability, the availability of dramatically higher landing energies, and the benefits this improvement provides. These include detection of buried defects, a sharper image for detection of surface physical defects, minimization of wafer charge enabling much longer inspections, and material contrast. These advantages are illustrated through a number of examples. High landing energy can damage certain wafer surfaces and these concerns are also discussed. Overall, high landing energy is a powerful new tool in the e-beam inspection tool box which should be aggressively adopted.

Full-Wafer Voltage Contrast Inspection for Detection of BEOL Defects

This paper details an application where E-beam inspection (EBI) can be used for 100% full wafer inspection, generally considered a mythical target for EBI. For process layers where the line-widths and defects of interest are large, very large pixel size and high scan frequency can be used, thereby making full wafer inspection feasible. The metal layers in the back-end-of-line fit this bill when scanned in voltage contrast (VC) mode. Shorts or opens at any previous layer connected to the surface nodes can cause a VC signal, therefore the electrical health of each wafer is assessed for multiple layers simultaneously across the full wafer. The advantage of this scan is that failure sites can be identified and somewhat localized well before wafer final test. This application is more appropriate for semi-mature technologies where there are few defects per wafer, and therefore a full wafer scan is needed to catch a reasonable number of defects. The challenge with this type inspection is in identification of the root cause. A number of studies to map VC defect strength to types of physical defects are described. These studies demonstrated that this technique successfully finds yield limiting defects, but not all yield limiting defects will be detected. A plan for how to use the VC inspection to find root cause is presented.

Application of E-beam hot spot inspection for early detection of systematic patterning problems to a FinFET technology

Early in-line detection of systematic patterning problems in technology development can dramatically improve a technology’s chance for success. By uncovering layout geometries that are difficult to implement, prompt action may be taken so that solutions are in place well before product chips that contain these and similar patterns enter the manufacturing line. If a solution is not in place, this could spell disaster for the product and perhaps even the technology. Ideally, product chips will work on the first lot, which is referred to as “first time right.” To help ensure this, a methodology for in-line detection of systematic patterning problems using E-beam hot spot inspection (EBHI) was developed. We review this methodology, including the latest enhancements. Pattern simulation tools and other sources are used to provide die locations with challenging geometries for evaluation. EBHI evaluates the patterning capability for these locations using modulated wafers. A multifunction team addresses any hot spots that fail within the process window. EBHI is then used to evaluate the solutions proposed by this team. Application of this methodology to a fin-shaped field effect transistor technology is described using examples from the fin and back end of line modules. These examples illustrate the full range of actions used to resolve patterning issues.

E-Beam Hot Spot Inspection for Early Detection of Systematic Patterning Problems for a 22 nm SOI Technology

Early detection of systematic patterning problems can provide a major boost for a technology team. Often in the past, these type defects might only be detected after functional test and subsequent failure analysis. At this point, three to six months of process development time have been lost and three to six months of defective hardware have been wasted. In this paper, a methodology for in-line detection of systematic patterning problems using E-beam hot spot inspection (EBHI) is introduced. Pattern simulation tools and other sources are used to recommend X, Y locations with challenging geometries for evaluation. EBHI evaluates the patterning capability for these locations using modulated wafers. A multifunction team addresses the hot spots that fail within the process window. EBHI is then used to evaluate the solutions proposed by this team. Often, additional data is necessary to determine the full yield impact. This methodology provided tremendous value for IBM’s 22 nm SOI technology. Several examples illustrating this point are presented. Line monitoring after the process windows have been established is also discussed.

Detection of Sub-Design Rule Physical Defects Using E-Beam Inspection

E-beam inspection provides an alternative approach to brightfield inspection for detection of otherwise difficult to detect physical defects. Advantages of E-beam inspection include superior resolution, the ability to classify defects using patch images, automatic filtering of prior level defects, and beam conditions for material contrast. For extremely small defects, which are becoming more common with each technology, brightfield inspection can fall short because of resolution limits. Either the defects are too small to even be detected or the defects are hidden among nuisance or other types of defects and cannot be binned out without SEM review. We present four examples of challenging defects that could not effectively be monitored with brightfield inspection and, therefore, were monitored with E-beam inspection. Throughput is a key limitation of E-beam inspection. Therefore, brightfield inspection should always be used for defection of physical defects when effective. To maximize the chance of success with brightfield inspection, E-beam inspection data may be used as a gold standard for development of the best optical inspection conditions. A methodology to do this is described and illustrated.

Alternative voltage-contrast inspection for pMOS leakage due to adjacent nMOS contact-to-poly misalignment

We propose an innovative voltage-contrast (VC) inspection approach for detection and verification of the process window for contact-to-poly overlaying. The method uses alternative scans for inline detection of leakage induced by underneath overlay drift. Conventional optical inspection with box-in-box or bar-in-bar test structures cannot accurately indicate the overall overlay performance for all chip locations as geometries continue to shrink. An e-beam inspection system with VC contrast imaging was introduced during a recent technology update. The alternative e-beam system with positive and negative charging modes was set up to perform dual scans for sensitive pMOS and nMOS detection. Although positive-mode scanning can detect pMOS leakage on the surface, it indicates a normal subsurface with no leakage. Defects can only be identified by another scan in negative mode to detect contact-to-poly misalignment in the neighboring nMOS. Leakage electrons affect each other as they spread through poly lines crossing p/nMOS. The principle and mechanisms for leakage defects were verified in a series of corrective actions for misalignment. The methodology allows inline detection instead of end-of-line electrical testing and de-layered analysis. This greatly shortens the response time and facilitates yield learning.

Illuminating extreme ultraviolet lithography mask defect printability

For the next few years, the extreme ultraviolet lithography (EUVL) community must learn to find mask defects using nonactinic inspection wavelengths. Nonactinic light cannot always determine the exact nature of the defect, whether it is a particle, pattern, or defect in the multilayer. It also cannot predict which defects will induce phase errors and which will induce amplitude errors on wafers. Correlating the signature of the defect as seen by a nonactinic inspection tool and on wafer resist image will inject essential knowledge into the nonactinic defect classification. This paper will explore the correlation between EUVL mask defect signatures detected (and not detected) at both 193 nm and e-beam inspection wavelengths and wafer-printable defects. The defects of interest will be characterized at mask level using atomic force microscopy and critical dimension scanning microscopy. Simulations will be deployed to explain the signatures illuminated by both EUVL and 193 nm exposures. This work addresses the gap between inspection sensitivity at nonactinic wavelengths and EUVL mask defect printability, and provides generalized understanding of how the two views differ.

Fast Inspection of Non-Visual Defects in the Wafer Surface Using Two Low-Energy E-Beam Sources

Although the electron-beam (e-beam) inspection can find the non-visual defects in the semiconductor devices under the fabrication procedure, it has a problem of low inspection speed. To resolve this problem, in this work, we have demonstrate the low-energy e-beam inspection using a tiny microcolumn as the e-beam source. The experimental result indicates that the non-visual defects in the wafer can be easily identified by measuring the e-beam current at the backside of the wafer. Since it is not difficult to make the multiple e-beam sources by packing many microcolumns, we can enhance the inspection many times by using the microcolumn e-beam sources.

Inspection of the TFT Devices Using the Low-Energy Electron Beam Emitted from the Microcolumn

The inspection of the TFT device for the LCD panel has been usually carried out by the large-scale electron column where the kinetic energy of the electron beam is higher than 10 kV, which has many disadvantages for the inspection. In this work, we replaced the bulky electron column with a tiny microcolumn and carried out the inspection of the TFT device. The result shows that the low-energy e-beam inspection can clearly observe the physical defects of the devices and also identify the abnormal electrical behavior caused by the defects in the device.

Process Optimization of Contact Module in NOR Flash Using High Resolution e-Beam Inspection

The inspection sensitivities and capture rate capabilities of high resolution e-beam inspection system with extracting and retarding mode are evaluated. E-beam with retarding mode inspection demonstrates better performance and reflects the wafer sort yield loss in contact failure items directly. After the contact module process optimization, the yield was improved almost two times above.

Voltage Contrast Inspection Methodology for Inline Detection of Missing Spacer and Other Nonvisual Defects

A test structure specifically designed to allow inline detection of missing spacer is introduced. Missing spacer is too small to be physically detected with any current inspection tool and therefore its existence must be flagged using voltage contrast for detection with an e-beam inspection system. The structure and methodology used to address this defect during the ramp of a recent technology is described. Key benefits include a dramatically faster learning cycle and much better signal-to-noise ratio for split experiment evaluation. Missing spacer is one example of a growing class of nonvisual defects which will greatly impact future semiconductor technologies. General principles for designing test structures to detect these defect types are discussed.

Patterned wafer defect density analysis of step and flash imprint lithography

Acceptance of imprint lithography for complementary metal-oxide semiconductor (CMOS) manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This article specifically focuses on this challenge presenting the current status of defect reduction in step and flash imprint lithography (S-FIL). The results of defect inspections of wafers patterned using S-FIL are summarized. The masks or templates used to imprint wafers for this study were designed specifically to facilitate automated defect inspection. The templates were made by employing CMOS industry standard materials and exposure tools. The primary wafer inspection was performed using a KLA Tencor-2132 (KT-2132) automated patterned wafer inspection tool. Additional imprint inspections were carried out on a KT-eS32 e-beam inspection system. The first section of the article provides a brief background of S-FIL technology. Next, the defect types and potential sources are described. Section III contains recent results demonstrating defect reduction below 5cm−2 and the result of a high resolution e-beam inspection that provide insight into sub-50-nm S-FIL specific defects. A brief summary concludes the article.