RIE-Induced VIA Defect Inspection Using In-line Voltage Contrast Technique – 0.18 µm Technology

Abstract

Optical inspection is used in large-scale manufacturing processes to identify the pattern defect. However, the capture rate of killer defects is low due to the resolution limit of optical inspection. The Voltage Contrast (VC) technique of Scanning Electron Microscope (SEM) was developed to detect killer defects. The VC electron beam inspection is a widely used method in the IC manufacturing industry for the monitoring and characterisation of electrical defects at an early stage. The major drawback of E-Beam inspection is low throughput. To enhance the chip yield, some defects should be detected and reduced in the early stage of fabrication. Herein, we present the Back End of Line (BEOL) fabrication with 0.18 µm process technology and the application of VC methodology to inspect electrical defects. The defects mostly occur due to marginal process window, which affects the etching and lithography process. These effects lead to metal shorts and partial etch of interconnect producing open VIA12. Using inline VC-SEM the invisible defects can be detected at an early stage and chip yield can be further improved.