Patterned wafer defect density analysis of step and flash imprint lithography

Abstract

Acceptance of imprint lithography for complementary metal-oxide semiconductor (CMOS) manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This article specifically focuses on this challenge presenting the current status of defect reduction in step and flash imprint lithography (S-FIL). The results of defect inspections of wafers patterned using S-FIL are summarized. The masks or templates used to imprint wafers for this study were designed specifically to facilitate automated defect inspection. The templates were made by employing CMOS industry standard materials and exposure tools. The primary wafer inspection was performed using a KLA Tencor-2132 (KT-2132) automated patterned wafer inspection tool. Additional imprint inspections were carried out on a KT-eS32 e-beam inspection system. The first section of the article provides a brief background of S-FIL technology. Next, the defect types and potential sources are described. Section III contains recent results demonstrating defect reduction below 5cm−2 and the result of a high resolution e-beam inspection that provide insight into sub-50-nm S-FIL specific defects. A brief summary concludes the article.