Dynamic Bias Research Articles

Low Voltage High Performance Comparator

A comparator has been proposed using the dynamic bias concept. The proposed comparator operates on low power with minimum delay. It describes the comparison of power and delay characteristics between the dynamic bias model, elzakker circuit and two stage dynamic comparator circuits. This is achieved by enhancing the total effective transconductance with in the circuit. All these circuits were simulated at 130nm technology with a supply voltage of 1.2V.

A Decade Frequency Range CMOS Power Amplifier for Sub-6-GHz Cellular Terminals

A wideband 65-nm CMOS power amplifier (PA) is presented, with a decade frequency range from 600 MHz to 6.0 GHz. In this frequency range, the output power exceeds 26.6 dBm and the power gain and power-added efficiency (PAE) exceed 18.1 dB and 49%, respectively. For a 7.5-dB peak-to-average-power-ratio (PAPR) long term evolution (LTE) signal at 1.9 GHz, the circuit provides an average output power of 19 dBm, with a PAE of 40%, and an adjacent channel leakage ratio (ACLR) exceeding −31 dBc. In LTE measurements at 5.9 GHz, the average output power, PAE, and ACLR are 18.5 dBm, 38.8%, and −30 dBc, respectively, using supply modulation and baseband predistortion. The wide bandwidth (BW) and high performance are achieved by introducing a dual output topology with an off-chip higher order output-matching network, combined with a positive feedback cross-coupled differential cascode amplifier stage. By using supply modulation and dynamic gate bias with an injection-locked PA, improved back-off efficiency, and acceptable out-of-band and in-band distortion is obtained. The integrated circuit occupies an area of 1.0 $\times $ 0.73 mm2 in standard 65-nm CMOS technology and uses a supply of 3.0 V.

Adaptive Robust Unscented Kalman Filter for AUV Acoustic Navigation.

Autonomous underwater vehicle (AUV) acoustic navigation is challenged by unknown system noise and gross errors in the acoustic observations caused by the complex marine environment. Since the classical unscented Kalman filter (UKF) algorithm cannot control the dynamic model biases and resist the influence of gross errors, an adaptive robust UKF based on the Sage-Husa filter and the robust estimation technique is proposed for AUV acoustic navigation. The proposed algorithm compensates the system noise by adopting the Sage-Husa noise estimation technique in an online manner under the condition that the system noise matrices are kept as positive or semi positive. In order to control the influence of gross errors in the acoustic observations, the equivalent gain matrix is constructed to improve the robustness of the adaptive UKF for AUV acoustic navigation based on Huber’s equivalent weight function. The effectiveness of the algorithm is verified by the simulated long baseline positioning experiment of the AUV, as well as the real marine experimental data of the ultrashort baseline positioning of an underwater towed body. The results demonstrate that the adaptive UKF can estimate the system noise through the time-varying noise estimator and avoid the problem of negative definite of the system noise variance matrix. The proposed adaptive robust UKF based on the Sage-Husa filter can further reduce the influence of gross errors while adjusting the system noise, and significantly improve the accuracy and stability of AUV acoustic navigation.

An experimental study on the sale of counterfeit products under monitoring policies

This study examines the decision behaviour of a seller who may sell either a genuine product or a deceptive counterfeit product under a monitoring policy characterised by an inspection frequency and a penalty level. A unique feature of selling deceptive counterfeit products is that the seller incurs significant losses when the deceptive counterfeit product is inspected, but enjoys significant gains if it is not. We conduct a laboratory experiment to investigate the seller’s behaviour regarding his/her selling strategy. In contrast to the standard theoretical predictions, we observe that the seller’s strategy exhibits a “deviate-to-equal-probability” effect, a diminishing marginal impact of the penalty level, and dynamic behavioural biases such as the “gambler’s fallacy” and speculation. A behavioural model is developed using bounded rationality and prospect theory to describe the observed behaviours, including the perception of the inspection probability in an inverse “S-shaped” pattern. Our results imply that, when designing effective monitoring policies, policymakers need to discreetly choose inspection frequencies depending on the penalty levels and to take into account sellers’ dynamic behavioural biases.

Macroeconomic determinants of credit risks: evidence from high-income countries

Purpose The purpose of this paper is to empirically assess the significant indicators of macroeconomic environment that influence credit risk in high-income countries. Design/methodology/approach The study employs the system generalized method of moments estimator to avoid the dynamic panel bias and endogeneity issues. Different indices of economic growth are used in each model in order to find the most significant proxy of the economic cycle that influences problem loans. The analysis is carried out using a sample of 49 developed countries covering a 16-year period (2000–2015). Findings The overall empirical results highlight that the development of industrial sectors and exports are the main drivers of loan performance in high-income countries. The findings specifically recommend adopting an expansionary fiscal policy to boost per capita income and potential productivity for the safety of the banking system. Practical implications The findings have direct practical applicability for stabilizing the financial system. The study recommends the government to increase the productivity of export-oriented industries in order to boost employment and increase the payment obligations of individuals and business firms. More importantly, it highlights the essentiality of perfect economic policy to control default risks. Originality/value To the best of the authors’ knowledge, this is the first empirical study that compares the relative effect of three alternative proxies of the economic cycle on credit risk and identifies the most significant proxy. The current study also empirically shows that industrial development could be one of the crucial factors to improve financial health in developed countries.

Recursive state estimation for two-dimensional shift-varying systems with random parameter perturbation and dynamical bias

In this paper, the state estimation problem is investigated for a class of two-dimensional (2-D) stochastic systems with shift-varying parameters. The stochasticity with the underlying system comes from three sources, namely, random parameter perturbations, dynamical biases and additive white noises. The measurement output is subject to the uniform quantization as a result of communication constraints on the sensors. The purpose of the addressed problem is to recursively estimate the system states with prescribed estimation performance in spite of the stochastic disturbances and the uniform quantizations. An augmented model is first constructed to combine the information about the state and the bias, and the dynamical evolution is subsequently discussed. Furthermore, through stochastic analysis and mathematical induction, the estimator design algorithm is developed to acquire certain upper bound on the estimation error variance and such an upper bound is then minimized in the matrix-trace sense. Moreover, the boundedness issue of the estimation errors is investigated via matrix inversion lemma and inductive analysis technique. Finally, the effectiveness of the proposed state estimation algorithm is validated on a typical 2-D system modeled by the well-known Darboux equation with extensive application potentials in industrial processes.

A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation

Energy-optimal operation is one of the key requirements of the Internet-of-Things (IoT) applications to increase battery life. In this article, using a combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB), the energy-optimal operation is achieved with a given fixed operating frequency determined by application demands. Based on the observation that the ratio of leakage power to dynamic power can be an accurate indicator for the optimal operating point, the proposed method dynamically tracks the minimum energy operating points by adjusting supply voltage and body bias with very low hardware and power overhead. A custom dc-dc converter for supply voltage regulation and charge pumps for body bias generation were implemented with the proposed method in a Cortex-M0 processor. Since SRAM is included in the same energy optimization loop as the processor, a custom SRAM was designed to match the processor speed. The design is fabricated in an Mie Fujitsu Semiconductor (MIFS) 55-nm deeply depleted channel (DDC) CMOS and the proposed approach achieves energy consumption within 4.6% of optimal at 1 MHz across five process corners and temperatures from -20 °C to 125 °C. The fabricated processor achieves 6.4 pJ/cycle at 0.55-V and 500-kHz clock frequency.

社交焦虑注意偏向的动态变化

社交焦虑注意偏向的动态变化

A differential class‐E power amplifier with dynamic body bias technique

AbstractA fully differential class‐E power amplifier (PA) for wireless body area network applications is presented in this article. A novel dynamic self‐adapting body bias (DSBB) technique is introduced to improve the switch‐on transition and on‐resistance characteristics of MOS transistors. The proposed circuit is fabricated in the TSMC 0.18‐μm RF CMOS process. Measurement results show that the DSBB PA achieves a power‐added efficiency (PAE) of 46.9% with an output power of 13.1 dBm at 900 MHz. Compared to the conventional body‐ground connection PA, PAE and output power are improved more than 6.6% and 4.2 mW, respectively.

A physical and versatile aging compact model for hot carrier degradation in SiGe HBTs under dynamic operating conditions

This paper presents a new physics-based compact model implementation for interface state creation due to hot-carrier degradation in advanced SiGe HBTs. This model accounts for dynamic stress bias conditions through a combination of the solution of reaction-diffusion theory and Fick’s law of diffusion. The model reflects transistor degradation in terms of base recombination current parameters of HiCuM compact model and its accuracy has been validated against results from long-term DC and dynamic aging tests performed close to the safe-operating-areas of various HBT technologies.

Short Circuit Capability and Short Circuit Induced $V_{\mathrm{TH}}$ Instability of a 1.2-kV SiC Power MOSFET

The withstand capability and threshold voltage ( $V_{\mathrm {TH}}$ ) instability of 1.2-kV silicon carbide (SiC) MOSFETs under repetitive short circuit (SC) tests are investigated. An SC test system is constructed to apply repetitive SC stress to SiC MOSFETs and measure the transfer $I$ – $V$ characteristics and gate-to-source leakage current ( $I_{\mathrm {GSS}}$ ) after each set of SC tests. To evaluate the SC capability, repetitive SC tests with different SC durations ( $t_{p}$ ) are conducted until device failure. The SC withstand time (SCWT) at 1000 SC cycles is found to be $\sim 3.3~\mu \text{s}$ . $V_{\mathrm {TH}}$ instability under repetitive SC tests prior to the device failure is characterized. A bidirectional $V_{\mathrm {TH}}$ shift behavior, i.e., negative shift at shorter $t_{p}$ and positive shift at longer $t_{p}$ , was revealed. The $V_{\mathrm {TH}}$ shifts under repetitive SC tests are attributed to the SC pulse process according to the results of high-temperature reverse bias (HTRB) and dynamic high-temperature gate bias (HTGB) tests. The underlying mechanisms of the complex $V_{\mathrm {TH}}$ shift behavior are explained in a unified framework by taking into account the junction temperature ( $T_{j}$ ) increase with longer $t_{p}$ . TCAD device simulation is used to help analyze the mechanisms.

Low power & high gain differential amplifier using 16 nm FinFET

A low noise, two- stage differential operational amplifiers are designed in 16 nm FinFET technology are presented. The proposed design would be applied in high-speed system on chips (SOCs). The low leakage current, low power dissipation and high current driving abilities of the FinFET are taken into realization with a basic analog building block of OPAMP. In this proposed design dynamic biasing technique is used for enhancing the slew rate of the OPAMP. The input common mode range (ICMR) can be increased and the gain stability is improved by this technique. The performance of a differential amplifier is analyzed using mixed mode device and circuit simulation on FinFET in sub-16-nm node technologies. It observed that by using the FinFET based OPAMP has common mode rejection ratio is 76 dB with improved performance regarding the area, power, and bandwidth. The proposed design has less 1/f noise and better performance that can replace conventional MOSFET in low power Nano circuits.

Robust adaptive divided difference filter based on forgetting factors and its applications

SummaryThis paper proposes robust and adaptive divided difference filters (RADDFs) based on forgetting factors which are robust to dynamic systems with biases or uncertainties. The RADDFs are founded on the principle of covariance matching. The robustness of RADDFs is reflected in that it amplifies the innovation covariance to compensate the effect of dynamic biases or uncertainties. The forgetting factor is adjusted adaptively. Then, the scalar forgetting factor is further extended to multiple forgetting factors. The proposed RADDFs are illustrated by Mars entry navigation system with atmospheric density uncertainty, lift over drag ratio uncertainty, and ballistic coefficient uncertainty. To validate the filter performance by multiple forgetting factors, a typical tight coupling nonlinear system with abrupt biases is used.

Joint Registration and Fusion of an Infrared Camera and Scanning Radar in a Maritime Context

The number of nodes in sensor networks is continually increasing, and maintaining accurate track estimates inside their common surveillance region is a critical necessity. Modern sensor platforms are likely to carry a range of different sensor modalities, all providing data at differing rates, and with varying degrees of uncertainty. These factors complicate the fusion problem as multiple observation models are required, along with a dynamic prediction model. However, the problem is exacerbated when sensors are not registered correctly with respect to each other, i.e., if they are subject to a static or dynamic bias. In this case, measurements from different sensors may correspond to the same target, but do not correlate with each other when in the same Frame of Reference (FoR), which decreases track accuracy. This paper presents a method to jointly estimate the state of multiple targets in a surveillance region, and to correctly register a radar and an Infrared Search and Track (IRST) system onto the same FoR to perform sensor fusion. Previous work using this type of parent-offspring process has been successful when calibrating a pair of cameras, but has never been attempted on a heterogeneous sensor network, or in a maritime environment. This article presents results on both simulated scenarios and a segment of real data that show a significant increase in track quality in comparison to using incorrectly calibrated sensors or single-radar only.

Bandwidth and Slew Rate Enhanced OTA With Sustainable Dynamic Bias

A bandwidth and slew rate (SR) enhanced operational transconductance amplifier (OTA) with proposed sustainable dynamic bias, transient detector and passive on-chip high-pass filter is presented in this brief. The proposed design is able to detect large-signal applied to the input of the amplifier and dynamically adjust its bias current to enhance both unity-gain bandwidth (UGB) and SR at the same time to achieve fast-settling behavior without overshoot and undershoot, along with high immunity against variations of supply voltage and bias current. Fabricated with a commercial 130-nm CMOS technology, the proposed design is verified by measurements that it is able to increase its SR by over 15 times, with more than 7.5 times reduction in its power consumption to attain fast settling time compared with a conventional design. Design considerations and an architectural comparison of the proposed design with another design with a different approach are also included in this brief to verify its performance and viability.

Dynamic Dual-Gate Bias Modulation for Linearization of a High-Efficiency Multistage PA

This paper investigates the linearization of high-efficiency multistage PAs through gate bias modulation derived from the envelope of the RF input signal. We show that separate control of the driver- and power-stage gate bias voltages allows for independent linearization of gain and phase. An iterative algorithm determines signal-dependent gate voltage functions that minimize amplitude-to-amplitude (AM/AM) and amplitude-to-phase (AM/PM) distortion, and is demonstrated on a 10-W high-efficiency X-band GaN monolithic microwave integrated circuit (MMIC) PA with a custom-designed hybrid dual-gate bias modulator. The noise power ratio (NPR) of a 5-MHz-wide signal is improved by as much as 9.4 dB compared to the PA with a static bias, without degradation in power-added efficiency (PAE) and gain. The measured average PAE improves from 19.9 % at 9.8-dB backoff by 0.8 points, with a saturated gain increase of 0.2 dB at 9.7 GHz. A long-term evolution (LTE) signal with different envelope statistics and a 10.6-dB peak-to-average power ratio (PAPR) is amplified with an adjacent channel power ratio (ACPR) improvement of up to 7.9 dB.

CRLB for Estimating Time-Varying Rotational Biases in Passive Sensors

In target tracking systems involving data fusion it is common to encounter sensor measurement biases that contribute to the tracking errors. There is extensive research into estimating sensor biases, but very little research into bias estimation in the dynamic case, meaning that biases that change over time are addressed. This paper investigates the means for and necessity of estimating bias rates of change in addition to constant sensor biases to reduce the errors in the state estimates. This is explored by comparing the Cramer–Rao lower bound and root-mean-square error of simultaneous target state and bias estimates for rotational biases with three-dimensional passive sensors with roll, pitch, and yaw biases. The present work models the dynamic biases as linearly varying over time. The iterated least squares method is used for the search of the maximum likelihood estimate, and is shown to be statistically efficient via hypothesis testing.

CMOS rectifier design for RFID chip with high sensitivity at low input power to be combined with an ultrasmall antenna

AbstractThis paper presents CMOS radio frequency (RF) rectifier circuit design for radio frequency identification (RFID) tag with integrated on‐chip antenna. The proposed design focuses on high sensitivity and high efficiency at low input power. The rectifier circuit was designed using Advanced Design System (ADS) software tool with the UMC130 process as a single‐ended rectifier structure in different topologies where sensitivity and efficiency enhancement techniques are applied. This work presents the performance of the proposed CMOS RF rectifier circuit in comparison with previously published works for 915 MHz and 5.8 GHz operating frequencies. For the 915 MHz band, the highest sensitivity of −19.8 dBm is provided by the adaptive threshold voltage compensation circuit with a power conversion efficiency of 9.843%. The 5.8 GHz band uses the adaptive threshold voltage compensation and dynamic bulk bias techniques providing the highest sensitivity of −16.8 dBm. Compared with other works in the literature, the proposed circuits offer greater sensitivity and can easily be matched with ultrasmall on‐chip antennas because of appropriate values of the input impedance.

Energy-Saving Dynamic Bias Current Control of Active Magnetic Bearing Positioning System Using Adaptive Differential Evolution

This paper proposes an evolutionary algorithm-based energy-saving control strategy to control a highly nonlinear and time-varying active magnetic bearing (AMB) positioning system that considers energy efficiency and control performance simultaneously. Most AMB control schemes use a bias current with a superimposed control current to improve the linearity and dynamic performance of the system. However, the bias current causes power losses even if no electromagnetic force is required. As such, a recurrent wavelet fuzzy neural network with adaptive differential evolution (RWFNN-ADE)-based dynamic bias current control strategy is proposed in this paper so as to minimize the energy consumed by an AMB without altering its positioning performance and robustness. To begin with, this paper analyzes the operation principle of the AMB positioning system with a differential driving mode. Subsequently, the proposed RWFNN-ADE control scheme, in which the control current and bias current are controlled by the RWFNN and ADE, respectively, is introduced in detail. Finally, the experimental results demonstrate the high-accuracy control and significant energy-saving performances of the proposed RWFNN-ADE-controlled AMB positioning system. In the tests corresponding to operation periods of 10 and 50 s, the energy improvements compared to the baseline values were 20.24% and 17.65%, respectively, in nominal cases, and 18.89% and 18.68%, respectively, in parameter variation cases, for the proposed control strategy.

Simple DC-Link Voltage Balancing Approach for Cascaded H-Bridge Rectifier with Asymmetric Parameters of Independent DC Loads

CHB is a suitable type of topology for synchronous rectifier application which has two or more independent DC loads. Focusing on the individual DC-link capacitor voltage balancing problems caused by asymmetric parameters of independent DC loads, this paper developed a new dual modulation signals based phase disposition pulse width modulation (PD-PWM) strategy using dynamic carrier bias allocation method. Its main idea is to allocate the bias of the carrier wave dynamically according to the balance situation of the system. Compared with the traditional modulation strategies, this method is more easily to be realized and has much stronger dynamic regulation ability. This modulation strategy is widely applicable to various types of CHB structures. A detailed analysis of the DC-link capacitor charge-discharge profile is performed, and an operation condition based dynamic bias allocation method is described using the cascaded H-bridge rectifier (CHBR) structure of five sub-modules as an example. A simulation model and an experiment platform are developed, and the feasibility and effectiveness of the modulation strategy are verified by simulation and experiment results.