Dynamic Random Access Memory Process Research Articles

Low sheet resistance buried metal bit line realized by high-temperature metal CVD process in vertical channel transistor array

With the continuous evolution of dynamic random access memory (DRAM) devices, there is a growing demand for increased storage density per unit area. In this work, we aim to create a high-density array of vertical channel transistors using advanced DRAM process technology. A thickness of SiO2 (X+3 nm) was determined for the protective layer, which shows the best-protecting effect. We employed CVD to grow thin Ti films on the array’s bottom. To reduce the resistance of the buried bit line (BBL), we formed a high-quality metal silicide using a thermal annealing process combined with self-align technology. Nanoprobe measurement results show an average resistance of approximately 60 Ω of the bit line of each cell transistor, where the low series resistance can improve device performance. Our work involved optimizing the protective layers and achieving high-performance BBLs, paving the way for the development of high-density DRAMs.

Implementation of rutile-TiO2 thin films on TiN without post-annealing through introduction of SnO2 and its improved electrical properties

Rutile-TiO2 has been actively studied as a high-k candidate for next-generation dynamic random-access memory (DRAM) capacitors due to its higher dielectric constant compared to commercially used ZrO2 and HfO2 based dielectrics. However, because the thermodynamic stabilization temperature of rutile-TiO2 is above 750 °C, which is not acceptable for the DRAM process, noble metal-based functional electrodes, such as RuO2 have been indispensably used for the formation of rutile-TiO2 thin films. The proposed method suggests the strategic introduction of Sn to reliably achieve mass production of rutile-TiO2 thin film on TiN electrodes. However, the atomic layer deposition (ALD) process with a commercially employed Sn precursor had issues such as requiring additional thermal process for crystallization due to low process temperature or generating a reducing by-product. Therefore, in this study, we realized rutile-TiO2 thin films on TiN electrodes without an additional post-thermal process using a new Sn precursor capable of high-temperature deposition. By employing an optimized Sn-doped TiO2 on seed layer, it was possible to implement a high dielectric constant of over 100, and the leakage current improvement effect was also confirmed. Therefore, the process presented in this study suggests a direction for future high-k research on next-generation DRAM capacitors.

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ

This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an alternative-data-bus (ADB) is employed to solve the frequency limit of the data bus. The proposed T-coil-based GDDR6 DRAM achieves 27 Gb/s/pin with 1.35 V in a DRAM process.

A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

The demand for high-performance graphics systems used for artificial intelligence, cloud game, and virtual reality continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. This article proposes a GDDR6 dynamic random access memory (DRAM) with a half-rate clocking architecture and optimized receiver and transmitter to improve high-speed operation. Furthermore, this article adopts a staggered PAD using the redistribution layer (RDL) to reduce the distance to four PADs; it enables the mitigation of bandwidth limitation of half-rate clocking, a lower phase mismatch, and a reduced propagation delay. The proposed half-rate clocking-based GDDR6 DRAM achieves 24 Gb/s/pin on a 1.35-V DRAM process. Also, the power-supply-induced-jitter (PSIJ) value is improved from 9.97 to 3.22 ps, compared to a GDDR6 design using a quarter-rate clocking. In addition, the phase mismatch of the proposed clock distribution network (CDN) is reduced compared to the conventional CDN, resulting in an improvement of the 3- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma $ </tex-math></inline-formula> value of the phase skew from 4.16 to 2.25 ps.

An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process

As the technology node of the dynamic random-access memory (DRAM) continues to decrease below the 10-nm-class, bit-cell failures due to the external environments have increased. As a result, DRAM vendors perform post package inspections to provide fault-free DRAMs to the end customers. However, post package inspections require considerable test costs. To overcome this issue, an in-DRAM built-in self-test (BIST) mechanism is implemented in this study as an alternative solution. Herein, we propose compact and high test-coverage features for the in-DRAM BIST that to resolve the area problem when applied to a commodity DRAM. The proposed BIST secures the same test coverage with a shorter time than the conventional BIST. The proposed BIST reduces the test time by 52% of the DDR BIST in functions with the same test coverages. Further, the implemented BIST can achieved an area overhead of 0.051% based on a 16Gb DDR4 DRAM in the second generation of the 10-nm-class DRAM process.

A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems

Dynamic random access memory (DRAM) reliability has become one of the critical issues in embedded systems, as DRAM process technology advances with the increase in bit error probability. Unfortunately, redundant error-correction code (ECC) chips cannot be applied to embedded systems since cores and DRAMs are tightly coupled without a dual in-line memory module (DIMM) slot to account for the form factor, cost, and limited pin count. Therefore, ECC parities are typically placed in the same physical array where the user and system data reside. This coexistence eventually deteriorates data locality, which could be the critical factor in DRAM performance degradation. To address this issue, we propose an ECC scheme called locality-aware compression (LoComp) which integrates a compression algorithm, DRAM data layout, and memory controller especially optimized for embedded systems. We focus on the locality of the dataset and its corresponding metadata, as well as spatial data locality in the design of DRAM data layout, which reduces the number of row activations. The major feature in a compression algorithm is adjusting the misalignment of data streams caused by the data packing in many embedded systems. Moreover, we specialize the memory controller to reduce DRAM access for ECC parities and compression flags. The core technologies for the memory controller are the adoption of a set of small caches for metadata and the support of partial write operation without changing the DRAM interface. LoComp+, an enhanced version of LoComp, further reduces DRAM access for metadata by placing the metadata close to the corresponding data. In the experiment, previous works increase the DRAM access time from 68% to over twice the value compared to ECC DIMM. Whereas, LoComp and LoComp+ show reduced performance degradation by 33% and 48%, respectively. In other words, LoComp and LoComp+ substantially improved performance from between 13% and 33% compared to previous embedded ECC schemes.

A Sub-1.0-V On-Chip CMOS Thermometer With a Folded Temperature Sensor for Low-Power Mobile DRAM

As Dynamic Random Access Memory (DRAM) supply voltages drop below 1 V with the scaling down of the process, it becomes increasingly difficult to construct a temperature sensor with sufficient accuracy to control self-refresh, without occupying significant area or consuming increased power. In this brief, we propose an on-chip CMOS thermometer with a temperature sensor, the output of which is divided into segments by a folding scheme. The slopes of these segments can be arranged to be the same or adjusted separately, as desired for the output. Implemented in a 29-nm DRAM process, the sensor operates from −40 °C to 95 °C at the supply voltage of 0.8 V, with a temperature sensitivity of −3.1 mV/°C between −40 °C and 35 °C, and −2.1 mV/°C between 35 °C and 95 °C. It has an area of 0.0016 mm2 and consumes less than 0.144 $\mu\text{W}$ .

A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

In this paper, a low-cost and low-leakage gate-first high-k metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> coupled with Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 μA/μm can be obtained for an OFF-state current of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> A/μm, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability.

Study on Bit Line TiCl4 TIN Process Optimization for Stack DRAM IDDS Standby Failure Improvement

Dynamic Random Access Memory (DRAM) plays an important role in semiconductor industry. For 0.13um stack DRAM (D13) process, Bit line (BL) is a critical loop and acts as a contact between active area (AA) and periphery area. Normally, BL consists of BL glue layer Ti/TiN and BL W. TiCl4 is applied for D13 BL glue layer Ti/TiN deposition. D13 suffers electrical drain-to-drain standby (IDDS) failure that means junction electrical leakage. Through further investigation, BL glue Ti/TiN have influence on AA Ti diffuse, and IDDS standby failure will be enhanced with deeper TiSix formation. In this study, we present the effect of TiCl4 glue TiN film's quality on D13 IDDS standby failure.

Chemical vapor deposition–physical vapor deposition aluminum plug process for dynamic random-access memory applications

The integrated chemical vapor deposition (CVD)–physical vapor deposition (PVD) Al plug process was successfully applied to capacitor-over-bit-line-type dynamic random-access memory process flow for the simultaneous formation of plugs and wires. The CVD-PVD Al film completely filled re-entrant vias with aspect ratios up to 10:1, and Al plugs showed lower via resistance compared with that of conventional W plugs. The PVD Al temperature can be as low as 350 °C, which is compatible with most low-dielectric-constant intermetal dielectric materials. However, outgassing from the intermetal dielectric was critical to complete via filling of the CVD-PVD Al film, and the conventional degassing process was insufficient for eliminating outgassing from hydrogen silsesquioxane. Sufficient baking after the via etching was effective for eliminating outgassing, and complete via filling was achieved.

Process Window Enlargement for Borderless Contact Formation by BPSG Stack Structure

Anomalous oxynitride loss after steam borophosphosilicate glass (BPSG) flow is observed for a borderless contact structure, and such loss engenders possible bit line shorts to word line. This phenomenon becomes more severe for BPSG film with higher phosphorous concentration. Phosphoric acid generation is deduced as the major mechanism. To enlarge process windows, a BPSG/undoped silicate glass stack has been proposed to withstand etch by acid. From practical application to 256 Mb dynamic random access memory process, this stack also shows a higher bit line contact yield and comparable contact sheet resistance with conventional stacks. More important, this technique could be fully integrated into incumbent ultralarge scale integrated technologies.

Overlay performance of SR lithography in 64M DRAM layers

Synchrotron radiation lithography is applied to the real dynamic random access memory process. Two full chip x-ray masks whose overlay accuracy is 19.2nm (x) and 26.4nm(y) are prepared. By using Canon x-ray stepper, total overlay accuracy less than 45nm is obtained.

Applicability test for synchrotron radiation x-ray lithography in 64-Mb dynamic random access memory fabrication processes

To evaluate the applicability of synchrotron radiation x-ray lithography (SRXL) in ultra-large-scale integration manufacturing processes, we simulate a part of a dynamic random access memory process using SRXL. Four levels of x-ray masks (field, gate, bit contact, and bit line), including fiducial patterns for coordinate/overlay measurement, alignment marks, and 0.4-μm-rule memory cells were fabricated using an i-line stepper. The maximum overlay error between the different level masks was 60–100 nm. In SRXL processes alignment errors of the x-ray stepper were 60–100 nm (3σ), and the overlay errors over a 20-mm-exposure field were 130–160 nm (‖mean‖+3σ) in most of alignment levels. Critical dimension control of 27–47 nm was obtained for gate length and contact hole diameter.

Particulate-contamination-free wafer-handling systems for gas, liquid and vacuum environments used in a 64 Mbyte dynamic random-access memory process

Devices which establish particle-free wafer handling for gas, liquid and vacuum environments used in a 64 Mbyte dynamic random-access memory (DRAM) process were developed. A non-contact handler was developed as a handling device for use in a gas environment, such as air or nitrogen, which keeps wafers clean without touching them through the mutual action of gas suction and blow-out. Also, a non-contact gas levitation track was developed for use in a gas environment, which levitates, transfers and guides wafers without any contact using the fluid force of gas blow-out with a very low velocity. A liquid levitation transport track was developed for use in a liquid environment, which transports wafers without exposing them to atmosphere using the fluid forces of liquid jets. An electrostatic chuck was developed as a device for use in a vacuum environment which holds a wafer by a Coulomb attractive force. This electrostatic chuck is used as the hand of a wafer handler and the holding system of a wafer stage. These devices were applied to actual manufacturing processes and it was confirmed that they are effective for reducing wafer contamination. Automation of the manufacturing line in the 64 Mbyte DRAM process for the future is attempted with these devices.

Effects of Various Pre‐Intrinsic and Phosphorus Diffusion Gettering Treatments Upon Quality of Czochralski Silicon Wafer Surface during a Simulated 4 Megabit Dynamic Random Access Memory Process

Effects of various preintrinsic and phosphorus diffusion gettering treatments upon quality of near‐surface region in Czochralski silicon wafers are studied during a simulated 4 Mb dynamic random access memory process. Denuded zone depth and bulk microdefect density are determined by synchrotron radiation section topography. Minority carrier lifetime and junction characteristics from test device structures were measured to determine overall gettering efficiency. A two‐step thermal anneal cycle before actual device processing resulted in formation of precipitates, dislocations, stacking faults, and a well‐defined denuded zone in samples with medium oxygen content only when a low‐temperature cycle at 775°C was followed by a high‐temperature one at 1150°C. The longest minority carrier lifetimes are observed in samples where very few or no defects are visible in the bulk of the wafer in the section topographs. Phosphorus gettering, however, was found to be effective for improving both minority carrier lifetime and junction properties.