Dynamic Random Access Memory Modules Research Articles

Intrinsic Run-Time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security †

Physical Unclonable Functions (PUFs) based on the retention times of the cells of a Dynamic Random Access Memory (DRAM) can be utilised for the implementation of cost-efficient and lightweight cryptographic protocols. However, as recent work has demonstrated, the times needed in order to generate their responses may prohibit their widespread usage. To address this issue, the Row Hammer PUF has been proposed by Schaller et al., which leverages the row hammer effect in DRAM modules to reduce the retention times of their cells and, therefore, significantly speed up the generation times for the responses of PUFs based on these retention times. In this work, we extend the work of Schaller et al. by presenting a run-time accessible implementation of this PUF and by further reducing the time required for the generation of its responses. Additionally, we also provide a more thorough investigation of the effects of temperature variations on the Row Hammer PUF and briefly discuss potential statistical relationships between the cells used to implement it. As our results prove, the Row Hammer PUF could potentially provide an adequate level of security for Commercial Off-The-Shelf (COTS) devices, if its dependency on temperature is mitigated, and, may therefore, be commercially adopted in the near future.

Runtime Memory Controller Profiling with Performance Analysis for DRAM Memory Controllers

The main memory system has become crucial not only because it has to meet an increasing bandwidth requirement, but also because it has to seamlessly support many concurrently executing applications. In order to improve memory performance, a memory controller with efficient arbitration is necessary. It is well known that memory performance is dependent on the memory access patterns. The offline performance analysis has difficulty analyzing the Dynamic Random Access Memory (DRAM) performance accurately because a huge set of trace patterns is needed. This paper proposes a novel profiler that is synthesized with a memory controller in order to monitor and analyze the memory controller performance at runtime. In this paper, five key metrics for performance evaluation are defined and they are monitored and evaluated at runtime by the proposed profiler. A prototype system with a processor core, a memory controller, DRAM modules, and peripheral devices are implemented on a field-programmable gate array (FPGA) board to carry out the experiments. It has been observed that the worst latency overhead differs for each benchmark. In addition, a new overall overhead estimation method is proposed to estimate the memory access latency overhead in time, and this method can be used to evaluate the performance of a certain memory arbitration method depending on running applications.

Retention-Aware DRAM Assembly and Repair for Future FGR Memories

Refresh operations consume substantial energy and bandwidth in high-density dynamic random-access memory (DRAM) memory. The trend of increasing refresh overhead limits the scalability of DRAM memory that refreshes all cells at the same rate, because the refresh rate setting depends on the worst-case weak cell manufactured in unstable process technology. To cope with this issue, fine-grained refresh (FGR) is proposed to eliminate the unnecessary refresh operations caused by minor weak cells. Even JEDEC's DDR4 DRAM specification announces the support of FGR, which is likely to evolve and become a standard in future DRAM. Unfortunately, according to our key observation, the effectiveness of FGR is greatly confined by the procedure of refresh-oblivious device integration because all memory devices within a module have to be controlled and refreshed in a lockstep way after the step of assembly. In this paper, we are the first to propose a holistic FGR-oriented DRAM optimization framework, retention-aware DRAM assembly and repair (RADAR), to enhance the effectiveness of FGR in DRAM modules. RADAR includes two novel techniques applicable at the stage of DRAM assembly. The first one is retention-aware device clustering that integrates the “compatible” devices to achieve low refresh rate through a preassembly testing and retention-aware matching method. The second technique, Microfix, exploits the hierarchical DRAM array structure and its redundancy to fix critical weak DRAM rows through fine-grained row and subarray remapping. With this optimization architecture, RADAR, the refresh overhead of DRAM dual in-line memory modules can be dramatically reduced as implied in the experiments.

Challenges of Memory Management on Modern NUMA System

Modern server-class systems are typically built as several multicore chips put together in a single system. Each chip has a local DRAM (dynamic random-access memory) module; together they are referred to as a node. Nodes are connected via a high-speed interconnect, and the system is fully coherent. This means that, transparently to the programmer, a core can issue requests to its node’s local memory as well as to the memories of other nodes. The key distinction is that remote requests will take longer, because they are subject to longer wire delays and may have to jump several hops as they traverse the interconnect. The latency of memory-access times is hence non-uniform, because it depends on where the request originates and where it is destined to go. Such systems are referred to as NUMA (non-uniform memory access).

Specific energy consumption of dynamic random access memory module supply chain in Taiwan

This study focuses on specific energy consumption (SEC) of all major energy consuming segments of the Dynamic Random Access Memory (DRAM) module supply chain, including 12” Si-wafer (ingot), wafer fabrication, integrated circuit (IC) assembly, IC testing, module assembly, and printed circuit board (PCB). Results show that energy consumption of a single unit of the end product from the DRAM supply chain is 4.67 kWh/PIC (PIC = a piece of DRAM module). For its annual shipments of 85,136,366 PIC/yr, the whole DRAM supply chain consumes a total of 397,331,726 kWh of energy, emitting 252,703 tons of CO2. The outcomes of this study provide baseline SEC of the DRAM supply chain that can be used while designing fabrication plants (hereafter referred to as “fabs”) in the future. We estimate that if all fabs in Taiwan achieve the same level of SEC as the best performer (i.e. lowest SEC level), annual energy savings and emissions reduction in Taiwan could be expected to reach 228,561,645 kWh of electricity and 149,426 tons of CO2 emissions, respectively.

Applying PSO-based BPN for predicting the yield rate of DRAM modules produced using defective ICs

Dynamic random access memory (DRAM) modules are an important component of electronic equipment, impacting the quality, performance, and price of the final product. A typical DRAM module is composed of DRAM integrated circuits (ICs). DRAM ICs of higher quality can be used to produce DRAM modules of higher quality. However, high-quality DRAM ICs are more costly. Some DRAM module manufacturers purchase batches of DRAM ICs containing defective units and then have the batch tested in order to select DRAM ICs for production of DRAM modules. This type of DRAM module is suitable only for products not intended for work in harsh environments or being sold in lower price markets. Due to the lower quality of the DRAM ICs, the actual quality of the DRAM module is not easily predicted. Predicting the yield rate of the DRAM module is thus an important issue for DRAM module manufacturers who purchase DRAM ICs of lower quality. This study uses a back-propagation neural network (BPN) to predict the yield rate of the DRAM modules produced using defective DRAM ICs. BPN is a very capable method and has been successfully applied across many fields. However, network parameters and input features differ depending on the application. Thus, a particle swarm optimization approach is proposed to obtain suitable parameters for the BPN and to select beneficial subsets of features which result in a better prediction of the DRAM module yield rate. The experimental results showed that it outperforms traditional stepwise regression analysis.

A strategy for improvement of the C<SUB align=right>pk of DRAM modules in the depanel process of PCBA

This paper is to improve the dimensional accuracy of Small Outline Dual Inline Memory Modules (SO-DIMMs), which is a kind of Dynamic Random Access Memory (DRAM) modules for notebook computer, in the depanel process. This study proposes the implementation of combining grey relation analysis with Statistical Process Control (SPC) analysis, so as to quickly search the result that progressive tool wear is the dominant parameters adversely influencing the accuracy in the depanel process. To resolve tool wear issue, this paper implements the pretreated milling for a certain working distance before practically proceeding the depanel process. The accuracy of products, therefore, appears to be feasibly controllable. Furthermore, this study adopts SPC analysis to evaluate the improvement effect, revealing that Cpk value dramatically increases from 0.788 to 2.175, and the tool life of mill can also be extended from milling of 25 to 45 panels. It has also been successfully implemented in an international factory, resulting in a yield of more than 1 million DRAM modules.