Dynamic Logic Family Research Articles

Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing

In this paper, we propose a non-traditional design of dynamic logic circuits using Fully-Depleted Silicon on Insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_t</i> ) to be adjustable (i.e., low-Vt and high-Vt states) by using the back gate bias. Our design utilizes the front and back gates of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like; NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like; half adder and full adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates.

A semantics and a logic for Fuzzy Arden Syntax

Fuzzy programming languages, such as the Fuzzy Arden Syntax (FAS), are used to describe behaviours which evolve in a fuzzy way and thus cannot be characterized neither by a Boolean outcome nor by a probability distribution. This paper introduces a semantics for FAS, focusing on the weighted parallel interpretation of its conditional statement. The proposed construction is based on the notion of a fuzzy multirelation which associates with each state in a program a fuzzy set of weighted possible evolutions. The latter is parametric on a residuated lattice which models the underlying semantic ‘truth space’. Finally, a family of dynamic logics, equally parametric on the residuated lattice, is introduced to reason about FAS programs.

Verification of dynamic bisimulation theorems in Coq

Over the last years, the study of logics that can update a model while evaluating a formula has gained in interest. Motivated by many examples in practice such as hybrid logics, separation logics and dynamic epistemic logics, the ability to update a model has been investigated from a more general point of view. In this work, we formalize and verify in the proof assistant Coq, the bisimulation theorems for a particular family of dynamic logics that can change the structure of a relational model while evaluating a formula. Our framework covers update operators to perform different kinds of modifications on the accessibility relation, the valuation and the evaluation point of a model. The benefits of this formalization are twofold. First, our results apply for a wide variety of dynamic logics. Second, we argue that this is the first step towards the development of a modal logic library in Coq, which allows us to mechanize many relevant results.

Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing

In this paper, novel circuit topologies for near-threshold computing (NTC) are proposed and evaluated. Three separate dynamic differential signaling based logic (DDSL) families are developed in a 130 nm technology to operate at 400 mV and 450 mV. The proposed logic families outperform contemporary CMOS and current-mode logic (CML) circuits implemented for near-threshold. The DDSL families are described as dynamic current-mode logic (DCML), latched DCML (LDCML), and dynamic feedback current-mode logic (DFCML). Simulation and analysis are performed through implementation of boolean functions and a 4×4 bit array multiplier. At a 450 mV supply voltage, the total power of the 4×4 DFCML multiplier is reduced to 0.95× and 0.009×, while the maximum operating frequency is improved by 1.4× and 1.12× as compared to, respectively, a CMOS and CML multiplier. The DCML multiplier consumes 1.48× the power while improving fmax by 1.65× as compared to a CMOS multiplier. A chain of four inverters implemented with the developed dynamic logic families exhibited an energy delay product (EDP) of 0.27× and 0.016× that of, respectively, CMOS and CML implementations. The mean noise margins, also evaluated with a chain of inverters, of DFCML and LDCML are at least 2.5× greater than that of CMOS.

Design and development of high performance MOS current mode logic (MCML) processor for fast and power efficient computing

Power dissipation and delay product have emerged to be crucial issue, which prove to decrease the performance of microprocessor. The MOS current mode logic (MCML) is an evolving logic family that is attracting interest owing to its high speed operation, reliable performance in comparison to the CMOS logic family. However, the MCML suffers from constant static power dissipation, which, if left unmanaged, would result in an inordinate energy requirement in large scale ICs. In order to resolve this challenge, the newly introduced system designed a modified MOS current mode logic (modified MCML) that has remarkable characteristics of lesser power dissipation, better switching frequency and greater processing speed. With the aim of achieving low power dissipation, the dynamic MOS current mode logic (dynamic MCML) is proposed. Dynamic MCML circuits integrate the benefits of MCML circuits with those that of the dynamic logic families for achieving great performance using a low-supply voltage along with low-power dissipation. The results obtained from simulation show that the newly introduced design model of dynamic MCML yields greater power conservation and higher processing speed in comparison with conventional CMOS technology, MCML and modified MCML with regard to power dissipation and power delay product.

High-performance dynamic elastic pipelines

In this paper, we will propose a new class of synchronous elastic pipelines called Dynamic Elastic Pipeline (DELP) that employs dynamic logic family and achieves improved throughput and elasticity. Since these pipelines are synchronous, they can be supported by Electronic Design Automation (EDA) flows, and as they are elastic, they benefit from elasticity of asynchronous circuits. In synchronous elastic circuits, elasticity is like that they are able to stretch or shrink the clock's pulses with a constant step. PS0 style, as well as conventional synchronous Static ELastic Pipeline (SELP) are used as the reference point, yet achieve remarkable improvements through novel control circuit optimizations. This paper concentrates on designing very fine-grain or gate-level pipelines in which the datapath is partitioned into stages with only a single level depth logic. Two new single-rail and dual-rail pipelines have been implemented and all implementations have been characterized by low-cost control structures and latchless design. Post-layout simulations in 90 nm technology reveal that the proposed dual-rail DELP design has 19.1% higher throughput than that of Williams’ PS0. Also, comparing to the synchronous SELP, our novel single-rail DELP achieves 52.4% higher throughput.

S.18.02 - Clinical studies on comorbidity of internet gaming disorders with mood, anxiety and personality disorders

In this paper, novel circuit topologies for near-threshold computing (NTC) are proposed and evaluated. Three separate dynamic differential signaling based logic (DDSL) families are developed in a 130 nm technology to operate at 400 mV and 450 mV. The proposed logic families outperform contemporary CMOS and current-mode logic (CML) circuits implemented for near-threshold. The DDSL families are described as dynamic current-mode logic (DCML), latched DCML (LDCML), and dynamic feedback current-mode logic (DFCML). Simulation and analysis are performed through implementation of boolean functions and a 4×4 bit array multiplier. At a 450 mV supply voltage, the total power of the 4×4 DFCML multiplier is reduced to 0.95× and 0.009×, while the maximum operating frequency is improved by 1.4× and 1.12× as compared to, respectively, a CMOS and CML multiplier. The DCML multiplier consumes 1.48× the power while improving fmax by 1.65× as compared to a CMOS multiplier. A chain of four inverters implemented with the developed dynamic logic families exhibited an energy delay product (EDP) of 0.27× and 0.016× that of, respectively, CMOS and CML implementations. The mean noise margins, also evaluated with a chain of inverters, of DFCML and LDCML are at least 2.5× greater than that of CMOS.

Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications

Near-threshold-voltage (NTV) circuit is to set the operating voltage near the threshold voltage of CMOS transistors to pursue the maximum energy efficiency. However, the characteristics for each logic family are quite different under NTV while comparing to its operation under normal supply voltage. In this paper, we proposed a new dynamic-static hybrid near threshold voltage adder design. The proposed keeper design can suppress the leakage current and avoid signal contention in the dynamic CMOS circuit, which lets the dynamic CMOS logic family can be adapted to NTV environment with excellent speed characteristics and higher energy efficiency. The proposed low leakage dynamic-static hybrid NTV 32-bits adder design can achieve the maximum energy efficiency with 161.7% enhancement as compared to the mirror adder under NTV with 0.3 V.

Single Event Resilient Dynamic Logic Designs

Dynamic logic families are commonly used in high speed applications, but they are susceptible to single event errors. This paper presents and evaluates three techniques of hardening dynamic logic--layout manipulation using charge sharing, addition of a feedback capacitor across the static inverter, and dual-rail domino logic with differential keepers. The layout-based design has better single event tolerance by sharing charge between NFET devices of the dynamic and static inverters; the design with a feedback capacitor makes the keeper more effective in recovering the hit node because of the increased propagation delay; the differential-keeper structure shows superior SET performance because the hit node could recover through the restoring path in the case of charge loss. These proposed designs along with the reference traditional keeper-based design were fabricated in a 130 nm technology node as shift register chains and then irradiated by heavy ion particles. Experimental results verified the mechanisms and effectiveness of these proposed designs.

Dynamic Current Mode Logic Realization of Digital Arithmetic Circuits

In this paper, we realize a high performance arithmetic circuits which is faster and have lower power consumption using a new dynamic logic family of CMOS and to analyze its performance for arithmetic circuits. This new dynamic logic family is known as Dynamic Current Mode Logic (DyCML). DyCML circuits combine the advantages of MOS current mode logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. A major advantage of the DyCML is the dynamic current source, which achieves smaller delays compared to the basic MCML circuits. Other advantages inherited from MCML are high performance and robustness to supply voltage scaling. DyCML gates reduce power dissipation by reducing the output voltage swing. We compare a set of arithmetic circuits implemented in Dynamic Current Mode Logic with the other dynamic logic styles. Simulation and test results show that DyCML circuits are superior to DDCVS logic styles in terms of power dissipation. A 2-bit multiplier, full adder & xor/xnor gate in DyCML style is fabricated in 180nm CMOS technology. 2-bit multiplier and a full adder dissipate 145.1 µW and 55.14 µW respectively at 40 MHz for a voltage swing of 1.2V in DyCML style.

CMOS Form of Wallace Range Exploitation Domino Logic Full Adder

The main objective of this project is to provide new low power solution for very large scale integration (VLSI) designer. Especially, this work focuses on the reduction of power dissipation, which is showing an ever increasing growth with the scaling down of the technology. Various technologies at the different level of the design process have been implemented to reduce power dissipation at the circuit, architectural and system level. It permits for commencement of analysis during a procedure block before its analysis section begins, and quickly performs a final analysis as shortly because the inputs are valid. This dynamic logic family is best suited to arithmetic circuits as a result of the important path is created of a protracted chain of cascaded inverting gates. Because the major advantage of this logic that is higher speed is discovered upon cascading, it’s most fitted for arithmetic circuits using submicron technology. Keyword: Domino Logic, Wallace Multiplier, Power Dissipation, Full Adder, CMOS Logic

An Extension of Distributed Dynamic Description Logics for the Representation of Heterogeneous Mappings

As a family of dynamic description logics, DDL(X) is constructed by embracing actions into the description logic X, where X represents well-studied description logics ranging from the ALC to the SHOIQ. To efficiently support automated interoperability between ontology-based information systems in distributed environments, we have to design an expressive mapping language to semantically understand resources from remote and heterogeneous systems. Distributed Dynamic Description Logics D3L(X) is a natural generalization of the DDL(X) framework, which is designed to model the distributed dynamically-changing knowledge repositories interconnected by semantic mappings and to accomplish reasoning in distributed, heterogeneous environments. In this paper, we propose an extension of Distributed Dynamic Description Logics D3L(X) and investigate the reasoning mechanisms in D3L(X).

Modified Low Power Dynamic Adder for High Performance

This paper proposes a modified form of the design for low dynamic power adder using a reset network in the CMOS dynamic logic family. The results show that the dynamic power reduces as compared to lower dynamic power logic and the domino logic. In this modified form of the low dynamic power adder, the logic outputs are reset to low during the pre-discharge phase which is the high input to the clock. The logic evaluation takes place when the clock input is low. The modified logic is better than domino logic since it does not require an inverter for cascading the gates. In Pre-discharging, resetting the output low prevents the problems of charge sharing and charge leakage associated with the other dynamic logic families and also it avoids the static power dissipation which exists in the low power dynamic logic. Also resetting the output low avoids the problem of high transition time from high level to low level which exists in circuits employing PMOS logic. The proposed circuit is a mix of PMOS logic and a dynamic logic. The proposed logic cell can be cascaded in a domino like fashion without the need of an inverter.

A Family of Dynamic Description Logics for Representing and Reasoning About Actions

Description logics provide powerful languages for representing and reasoning about knowledge of static application domains. The main strength of description logics is that they offer considerable expressive power going far beyond propositional logic, while reasoning is still decidable. There is a demand to bring the power and character of description logics into the description and reasoning of dynamic application domains which are characterized by actions. In this paper, based on a combination of the propositional dynamic logic PDL, a family of description logics and an action formalism constructed over description logics, we propose a family of dynamic description logics DDL(X @) for representing and reasoning about actions, where X represents well-studied description logics ranging from the to the , and X @ denotes the extension of X with the @ constructor. The representation power of DDL(X @) is reflected in four aspects. Firstly, the static knowledge of application domains is represented as RBoxes and acyclic TBoxes of the description logic X. Secondly, the states of the world and the pre-conditions of atomic actions are described by ABox assertions of the description logic X @, and the post-conditions of atomic actions are described by primitive literals of X @. Thirdly, starting with atomic actions and ABox assertions of X @, complex actions are constructed with regular program constructors of PDL, so that various control structures on actions such as the "Sequence", "Choice", "Any-Order", "Iterate", "If-Then-Else", "Repeat-While" and "Repeat-Until" can be represented. Finally, both atomic actions and complex actions are used as modal operators for the construction of formulas, so that many properties on actions can be explicitly stated by formulas. A tableau-algorithm is provided for deciding the satisfiability of DDL(X @)-formulas; based on this algorithm, reasoning tasks such as the realizability, executability and projection of actions can be effectively carried out. As a result, DDL(X @) not only offers considerable expressive power going beyond many action formalisms which are propositional, but also provides decidable reasoning services for actions described by it.

A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip–Flops With Embedded Logic

This paper presents several efficient architectures of dynamic/static edge-triggered flip-flops with a compact embedded logic. The proposed structure, which benefits from the overlap period, fixes most of the drawbacks of the dynamic logic family. The design issues of setting the appropriate overlap period for this architecture are explained. The proposed overlap-based approach is compared with several state-of-the-art dynamic/static logic styles in implementing a 4-bit shift register and an odd-even sort coprocessor using different CMOS technologies. The simulation results showed that the overlap-based logic cells become much more efficient when the complexity of their embedded logic function increases. Moreover, this approach improves static power consumption, which makes it even more efficient in below 0.18 ¿m CMOS technologies.

High performance low power CMOS dynamic logic for arithmetic circuits

This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies.

Dynamic differential self-timed logic families for robust and low-power security ICs

This paper describes two new dynamic differential self-timed logic families that can be used either to implement low-power security components or low-power high-speed self-timed circuits. Electrical simulations in 0.13 μm partially depleted (PD) SOI CMOS under a V dd of 1.2 V have shown that the substitution box (S-box), a module of the Khazad cipher algorithm, implemented with the improved feedback low swing current mode logic (IFLSCML) features a power consumption standard deviation almost five times smaller than that of the self-timed DDCVSL one, while consuming 37% less. On the other hand, the 8b CLA implemented with dynamic differential swing limited logic (DDSLL) features a power delay product about 19% lower than that of its counterpart implemented with self-timed DDCVSL.

Fast Feedthrough Logic: A High Performance Logic Family for GaAs

A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input signals arrive. A modified version of this logic, where the function and its complement are implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are reset to low during the high phase of the clock and evaluated during the low phase of the clock. Resetting to low alleviates the problems of charge sharing and leakage current associated with the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like fashion without a need for the intervening inverters. We employ this novel concept to design several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other published works in terms of device count, area, delay, clock rate and power consumption. The results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition, our FTL design compares very well with the standard CMOS technology. FTL gates are fully compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be included in a DCFL standard cell library for improving cell-based ASIC performance. To match the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining the FTL blocks. Comparisons with the other published results demonstrate the superior performance of our dynamic latch.

Low-power high-performance arithmetic circuits and architectures

A new class of dynamic differential logic families, swing limited logic (SLL), is proposed for low-power high-performance applications. Two implementations of SLL, short-circuit current logic (SC/sup 2/L) and clock-pulse controlled logic (CPCL), are designed. Low power is achieved by aggressively reducing logic swing. Using a 0.35-/spl mu/m CMOS technology and a nominal supply voltage of 3.3 V, an SC/sup 2/L 8-bit carry ripple adder (CRA) is implemented. It offers an order of magnitude less energy-delay product than several other logic families. Furthermore, two multipliers are constructed to demonstrate how SLL can be used in large circuit applications.

Dynamic current mode logic (DyCML): a new low-power high-performance logic style

This paper introduces a new reduced swing logic style called dynamic current mode logic (DyCML) that reduces both gate and interconnect power dissipation. DyCML circuits combine the advantages of MOS current mode logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. Unlike CML circuits, DyCML gates do not have a static current source, which makes DyCML a good candidate for portable devices and battery-powered systems. Simulation and test results show that DyCML circuits are superior to other logic styles in terms of power and delay. A 16-bit DyCML carry look-ahead adder (CLA), fabricated in 0.6-/spl mu/m CMOS technology, attains a delay of 1.24 ns and dissipates 19.2 mW at 400 MHz.