Dynamic differential self-timed logic families for robust and low-power security ICs

Abstract

This paper describes two new dynamic differential self-timed logic families that can be used either to implement low-power security components or low-power high-speed self-timed circuits. Electrical simulations in 0.13 μm partially depleted (PD) SOI CMOS under a V dd of 1.2 V have shown that the substitution box (S-box), a module of the Khazad cipher algorithm, implemented with the improved feedback low swing current mode logic (IFLSCML) features a power consumption standard deviation almost five times smaller than that of the self-timed DDCVSL one, while consuming 37% less. On the other hand, the 8b CLA implemented with dynamic differential swing limited logic (DDSLL) features a power delay product about 19% lower than that of its counterpart implemented with self-timed DDCVSL.